- Aug 29, 2004
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1) The functional specification for the Athlon 64 that I got off of AMD's website indicates that only 2x, 3x, 4x, and 5x HyperTransport multiplier are available. Similarly, the functional spec says that memory speeds of 100, 133, 166 and 200 are available (this translates to
1:2, 2:3, 5:6, and 1:1 mem:fsb ratios). Assuming that the logic controlling these multipliers is internal to the CPU, how is it possible for motherboards (such as the DFI Lanparty NF3 250gb) to different multipliers such as 2.5x Hypertransport or 4:5 mem:fsb.
2) I would assume that the memory controller portion of the Northbridge (buffers, open page logic, etc.) operates at the memory frequency specified by the mem:fsb ratio. If this is so, is there any logic within the Northbridge (or the chip for that matter) that operates at exactly the fsb frequency unmodified by any multipliers/dividers? Most likely I would think that Hypertransport related logic that operates at the fsb before getting multiplied up to the proper 2x/3x/4x/5x rate. However, it is possible that this processing is done in the CPU core (running according to CPU multipler) and/or the memory controller.
3) Depending on the answer to the second question, it may be that the only lmiting factor in overclocking the fsb (assuming HTT, memory, and CPU ratios are reduced accordingly) is the on chip PLL. The PLL is a part of the chip that multiplies up the input FSB to some high frequency from which all other necessary frequencies (CPU, HTT, memory, etc.) are derived. If it is true that there is no actually logic that runs at the FSB speed, would it be possible to, for example, jack up the FSB to 400 while halving the HTT, CPU, and memory ratios? Remeber that Athlon64 CPU multiplier can be decreased but not increased. For example, if CPU is stock 10x200=2000, could you double FSB and halve multplier to get 5x400=2000. At this point, you could increase the multiplier 0.5x at a time to increase frequency in 200mhz increments. This would not require faster memory, or a southbridge that can handle an oversped HTT link.
1:2, 2:3, 5:6, and 1:1 mem:fsb ratios). Assuming that the logic controlling these multipliers is internal to the CPU, how is it possible for motherboards (such as the DFI Lanparty NF3 250gb) to different multipliers such as 2.5x Hypertransport or 4:5 mem:fsb.
2) I would assume that the memory controller portion of the Northbridge (buffers, open page logic, etc.) operates at the memory frequency specified by the mem:fsb ratio. If this is so, is there any logic within the Northbridge (or the chip for that matter) that operates at exactly the fsb frequency unmodified by any multipliers/dividers? Most likely I would think that Hypertransport related logic that operates at the fsb before getting multiplied up to the proper 2x/3x/4x/5x rate. However, it is possible that this processing is done in the CPU core (running according to CPU multipler) and/or the memory controller.
3) Depending on the answer to the second question, it may be that the only lmiting factor in overclocking the fsb (assuming HTT, memory, and CPU ratios are reduced accordingly) is the on chip PLL. The PLL is a part of the chip that multiplies up the input FSB to some high frequency from which all other necessary frequencies (CPU, HTT, memory, etc.) are derived. If it is true that there is no actually logic that runs at the FSB speed, would it be possible to, for example, jack up the FSB to 400 while halving the HTT, CPU, and memory ratios? Remeber that Athlon64 CPU multiplier can be decreased but not increased. For example, if CPU is stock 10x200=2000, could you double FSB and halve multplier to get 5x400=2000. At this point, you could increase the multiplier 0.5x at a time to increase frequency in 200mhz increments. This would not require faster memory, or a southbridge that can handle an oversped HTT link.
