(see page 25)
In figure A, aren't x, y, and z always going to be the same? Why do they have 3 NMOS transistors and 3 signals instead of just one?
None of the outputs are ever pulled up. Would they be pulled up by the PMOS transistors on the inputs to more multi-drain logic? If you wanted to interface to "regular" logic, would you have to put a (ratioed) pull-up on the outputs from a circuit like Figure B?
What is the purpose of the bottom-rightmost transistor, which has nothing connected the drain?
Hopefully I'm not missing something simple like in the dynamic logic question
.
In figure A, aren't x, y, and z always going to be the same? Why do they have 3 NMOS transistors and 3 signals instead of just one?
None of the outputs are ever pulled up. Would they be pulled up by the PMOS transistors on the inputs to more multi-drain logic? If you wanted to interface to "regular" logic, would you have to put a (ratioed) pull-up on the outputs from a circuit like Figure B?
What is the purpose of the bottom-rightmost transistor, which has nothing connected the drain?
Hopefully I'm not missing something simple like in the dynamic logic question