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Mosfet slow fall time

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I wish you had a circuit diagram or something and specified what type of FET it was.

But if I had to take a wild guess, I would assume the FET was in a passgate configuration (input at drain, output at source, control at gate) and you're using a PFET device. In that case we will see a slow fall time mainly because the transistor is entering cutoff since it's not maintaining the gate to source threshold voltage.
 
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are you driving it directly from a MCU output? is there a high value resistor from the gate->ground?

ideally you'd dump charge into the gate as quickly as possible when you want to turn it on and suck charge out of it when you want it to turn off.
 
PottedMeat said:
are you driving it directly from a MCU output? is there a high value resistor from the gate->ground?

ideally you'd dump charge into the gate as quickly as possible when you want to turn it on and suck charge out of it when you want it to turn off.
Click to expand...

there is a 10K pull down at the gate....
 
Does it look like this?

fet.PNG


There are a few reasons for the RC decay you are seeing, but it would help to know some more about the circuit. If you really want to do some analysis, answer the following questions to the best of your ability and I'll talk you through it:

  1. What is the magnitude of the power supply rail?
  2. What is the amplitude of the MCU output?
  3. What size is the resistor?
  4. What are the specs of the LED? If you don't know, what color is the LED? If you don't know the model, knowing the color can typically get you a first order approximation of the forward voltage and possibly the current if it's a standard 3/5mm LED.
  5. Which transistor are you using?
  6. What frequency are you pulsing the LED?
And for extra credit:

  1. Do you know the edge rate of the microcontroller signal at the gate of the FET?
  2. Are you viewing the waveforms with a scope? If so, how much bandwidth does your scope have?
 
It seems he uses an N mosfet with the led connected at the source and perhaps the resistor in the drain. Maybe the miller effect is at play, i am just guessing with out a circuit diagram.
A circuit diagram with voltages (MCU and drain) is really needed here.
 
OP, is this your schematic?

fet2.PNG


If so, you need to put the LED on the other side of the FET like I showed in my previous schematic. The channel will cut off too soon in this configuration because the Vgs is now dependent on the forward voltage of the diode. It's not necessarily the problem, but without any other information I'm not sure what to tell you.
 
Vertical mosfets have routinely up to 2 nF input capacitance , so with a 10K
pull down resistor it yield about 20uS time constant T , so the pulse
frequency can not be lower than the inverse of 2pi.T that s about
1/(6 x 2 x 10^-5) = 8333 Hz .

According to the step curves at input and the output result , the driving
circuit has no trouble feeding the posisitive step current while it doesnt
sink adequatly the gate charge ; with the 10K resistor being of little help.
 
Abwx said:
Vertical mosfets have routinely up to 2 nF input capacitance , so with a 10K
pull down resistor it yield about 20uS time constant T , so the pulse
frequency can not be lower than the inverse of 2pi.T that s about
1/(6 x 2 x 10^-5) = 8333 Hz .

According to the step curves at input and the output result , the driving
circuit has no trouble feeding the posisitive step current while it doesnt
sink adequatly the gate charge ; with the 10K resistor being of little help.
Click to expand...

It's being driven with a cmos driver. The time constant you calculated would only be relevant if the microcontroller tri-states its output pin in order to let the pulldown resistor drain the gate charge, which is not the case. Superposition of the node means the 10k is doing practically nothing other than preventing it from floating.

TuxDave already came up with the most likely scenario. We're simply waiting on more information to confirm. The configuration of the FET is almost certainly the issue, not the sink capability of the microcontroller.
 
MrDudeMan said:
It's being driven with a cmos driver. The time constant you calculated would only be relevant if the microcontroller tri-states its output pin in order to let the pulldown resistor drain the gate charge, which is not the case. Superposition of the node means the 10k is doing practically nothing other than preventing it from floating.

TuxDave already came up with the most likely scenario. We're simply waiting on more information to confirm. The configuration of the FET is almost certainly the issue, not the sink capability of the microcontroller.
Click to expand...


If the Led is connected according to trhe second schematic ,
that is at the source , the driver can have trouble reaching
the gate/source threshold voltage since the source is floating,
hence requiring even more gate voltage in respect of the ground.

If the Cmos driver has enough current sink capability it could
then easily brought the gate to ground potential , switching
the unperfectly conducting device even faster than with the first
arrangement.

Besides , we still dont know the pulse width and frequency ,
so it s somewhat early to make a guess other than the one
that the OP lack of precisions is perhaps deliberate....🙂
 
It isn't doing what you think it is in the waveform you posted. When you turn off the fet the only thing left to discharge what remains is the scope probe, and that takes a little bit of time depending on the probe , wire length and settings, compensate for that and you don't have the slow turn off that you thought you had.
 
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