More on CSI

[Viditor]

ZDNet article

It seems a bit dissapointing...the goals for CSI were:
1. Allowing both Itanium and Xeon to drop into the same system board interchangeably
2. Allow direct access to system Ram and bypass the FSB

Point 2 still appears to be on track, but point 1 seems to have gone by the wayside.

Rich Marcello (Mngr HP Critical Server Group): "The CSI implementations are 95 percent the same, but there's a little bit of difference there. For that reason, we'll be close but not exactly the same," he said. However, they will be similar enough that some joint design work can be shared, he added

This also means that CSI will be released in 2 phases...the first in late 2008 will be for Itanium only, the second (Xeon version) will be sometime in 2009.

 

[myocardia]

All I can say is it took them long enough. Since it takes 5 years to develop each architecture, that means that Intel had absolutely no idea what AMD was going to come out with, concerning the Athlon 64's. But, think about it. Can you imagine what a Conroe would be like, with an integrated memory controller? And since it will probably be dual-core, all I can say is "Wow, that's gonna rock".

 

[Viditor]

Originally posted by: myocardia
All I can say is it took them long enough. Since it takes 5 years to develop each architecture, that means that Intel had absolutely no idea what AMD was going to come out with, concerning the Athlon 64's. But, think about it. Can you imagine what a Conroe would be like, with an integrated memory controller? And since it will probably be dual-core, all I can say is "Wow, that's gonna rock".

Actually, by the time it comes out it will most likely be at least quad core (if not 8 cores).
Keep in mind that we're talking 2-3 years from now...then think back to what was available 3 years ago.

 

[zsdersw]

So let me get this straight. I've never heard you say anything good about Itanium, Viditor.. and now you're disappointed that it won't be exactly drop-in compatible with Xeons and CSI? What's going on here?

 

[Viditor]

Originally posted by: zsdersw
So let me get this straight. I've never heard you say anything good about Itanium, Viditor.. and now you're disappointed that it won't be exactly drop-in compatible with Xeons and CSI? What's going on here?

OK, I'll help you get it straight...again.
CSI had 2 major design goals...1 will not happen. OK?

 

[myocardia]

Originally posted by: Viditor

Originally posted by: myocardia
All I can say is it took them long enough. Since it takes 5 years to develop each architecture, that means that Intel had absolutely no idea what AMD was going to come out with, concerning the Athlon 64's. But, think about it. Can you imagine what a Conroe would be like, with an integrated memory controller? And since it will probably be dual-core, all I can say is "Wow, that's gonna rock".

Actually, by the time it comes out it will most likely be at least quad core (if not 8 cores).
Keep in mind that we're talking 2-3 years from now...then think back to what was available 3 years ago.

Haha, when I reread what I had written the first time, I noticed that myself. I had meant quad-core. I just don't get a chance to type that very often. Practicing>> quad-core, quad-core, quad-core...

 

[Maximilian]

Sweet.

 

[Furen]

Originally posted by: zsdersw
So let me get this straight. I've never heard you say anything good about Itanium, Viditor.. and now you're disappointed that it won't be exactly drop-in compatible with Xeons and CSI? What's going on here?

Being allowed to use either Xeons or Itaniums in the same platform would do great things for consumer choice and the cost of Itanium infrastructure. Itanium is very expensive because, among other things, it requires its own customized system designs. I'm not a big fan of Itanium but being able to go Itanium if I so desired (without a massive increase in cost) would certainly be attractive. It would also be a huge help to the "smaller" Itanium OEMs (ie. SGI, Bull, etc), since they could broaden their portfolio without incurring much higher expenses.

 

[zsdersw]

Originally posted by: Viditor
OK, I'll help you get it straight...again.
CSI had 2 major design goals...1 will not happen. OK?

No, that doesn't clear anything up. If a design goal is aimed at a processor that you've had nothing good to say about, why should the goal not happening be a disappointment for you?

 

[zsdersw]

Originally posted by: Furen

Originally posted by: zsdersw
So let me get this straight. I've never heard you say anything good about Itanium, Viditor.. and now you're disappointed that it won't be exactly drop-in compatible with Xeons and CSI? What's going on here?

Being allowed to use either Xeons or Itaniums in the same platform would do great things for consumer choice and the cost of Itanium infrastructure. Itanium is very expensive because, among other things, it requires its own customized system designs. I'm not a big fan of Itanium but being able to go Itanium if I so desired (without a massive increase in cost) would certainly be attractive. It would also be a huge help to the "smaller" Itanium OEMs (ie. SGI, Bull, etc), since they could broaden their portfolio without incurring much higher expenses.

Yes, Itanium would certainly benefit from CSI if it were drop-in compatible with Xeons.. but I think there's still a benefit to Itanium even if it isn't. The platforms will be similar enough to lower the cost significantly.

 

[Kyanzes]

Originally posted by: myocardia
All I can say is it took them long enough. Since it takes 5 years to develop each architecture, that means that Intel had absolutely no idea what AMD was going to come out with, concerning the Athlon 64's. But, think about it. Can you imagine what a Conroe would be like, with an integrated memory controller? And since it will probably be dual-core, all I can say is "Wow, that's gonna rock".

You can't seriously say that. I bet there are dozens of Intel payed guys working at AMD to make sure they get all the info they ever need. Not to mention that all companies are obliged to give out info on their ongoing projects because of military application interests. And when the info is out, it's out. They also have obligations to inform long term partners. And ofc there's the human factor, people talk a lot. I can imagine that there are certain astonishing secrets being kept (not talking about AMD here) by certain individuals / agencies / governments etc. But there can't be too many. Remember the Rosenbergs. I mean if anything, that was classified stuff.

 

[myocardia]

Originally posted by: Kyanzes
You can't seriously say that. I bet there are dozens of Intel payed guys working at AMD to make sure they get all the info they ever need. Not to mention that all companies are obliged to give out info on their ongoing projects because of military application interests. And when the info is out, it's out. They also have obligations to inform long term partners. And ofc there's the human factor, people talk a lot. I can imagine that there are certain astonishing secrets being kept (not talking about AMD here) by certain individuals / agencies / governments etc. But there can't be too many. Remember the Rosenbergs. I mean if anything, that was classified stuff.

Yeah, both companies have schematics of each other's cpu's, before they are released. That's why it will have taken Intel, the largest manufacturer of cpu's on the planet, 5 years (also known in the cpu world as an entire development cycle) to come up with a functioning integrated memory controller.

Oh, and that's also why AMD wasn't worried at all about the upcoming Conroes, at least until they started showing up in the hands of reviewers, starting at CES of this year.

 

[Viditor]

Originally posted by: Furen

Originally posted by: zsdersw
So let me get this straight. I've never heard you say anything good about Itanium, Viditor.. and now you're disappointed that it won't be exactly drop-in compatible with Xeons and CSI? What's going on here?

Being allowed to use either Xeons or Itaniums in the same platform would do great things for consumer choice and the cost of Itanium infrastructure. Itanium is very expensive because, among other things, it requires its own customized system designs. I'm not a big fan of Itanium but being able to go Itanium if I so desired (without a massive increase in cost) would certainly be attractive. It would also be a huge help to the "smaller" Itanium OEMs (ie. SGI, Bull, etc), since they could broaden their portfolio without incurring much higher expenses.

Exactly...CSI was supposed to allow for a clean upgrade path from the Xeon (though the software migration still would remain as the biggest hurdle there).
One thing I'm quite surprised about is that Intel has not yet opened the standard to 3rd party developers (though it may be too early and they haven't yet defined it completely). If Intel has any hope at all of competing with Torrenza, I would think this would be quite necessary...

 

[Viditor]

Originally posted by: myocardia

Originally posted by: Kyanzes
You can't seriously say that. I bet there are dozens of Intel payed guys working at AMD to make sure they get all the info they ever need. Not to mention that all companies are obliged to give out info on their ongoing projects because of military application interests. And when the info is out, it's out. They also have obligations to inform long term partners. And ofc there's the human factor, people talk a lot. I can imagine that there are certain astonishing secrets being kept (not talking about AMD here) by certain individuals / agencies / governments etc. But there can't be too many. Remember the Rosenbergs. I mean if anything, that was classified stuff.

Yeah, both companies have schematics of each other's cpu's, before they are released. That's why it will have taken Intel, the largest manufacturer of cpu's on the planet, 5 years (also known in the cpu world as an entire development cycle) to come up with a functioning integrated memory controller.

Oh, and that's also why AMD wasn't worried at all about the upcoming Conroes, at least until they started showing up in the hands of reviewers, starting at CES of this year.

To be fair, integrated memory controllers weren't necessary (or even desirable) for the Netburst architecture...
In addition, Whitefield was originally scheduled to be released next year with CSI (and both design points). It's cancellation was due in a large part to Conroe's development (Intel said they were reassigning the Whitefield teams to Core2Duo).

 

[dmens]

Originally posted by: Viditor
To be fair, integrated memory controllers weren't necessary (or even desirable) for the Netburst architecture...
In addition, Whitefield was originally scheduled to be released next year with CSI (and both design points). It's cancellation was due in a large part to Conroe's development (Intel said they were reassigning the Whitefield teams to Core2Duo).

decreased load-to-use latency would have been quite useful for P4, considering its philosophy of releasing a shitstorm of speculation attempts.

i dont know why you insist csi will not accomodate both ia64 and x86. the term "95% the same" doesn't mean that at all. designers can tape out with logic for both platforms, and switch off the parts not required. simple enough.

also, whitefield was supposed to use merom cores, so its cancellation had nothing to with merom's development. that was all internal politics.

as for CSI being an open protocol to compete against the mysterious torrenza, that may or may not happen. but it seems AMD is going for the in-house platform route themselves. they closed down at least one startup working on a HT plugin that i know of, with threats of legal action. seems like they want to use ATI to develop their own socket drops. i dont see the logic behind declaring open CSI to be the only chance intel has to compete with a non-existent platform with vague benefits.

 

[BitByBit]

Originally posted by: myocardia
Can you imagine what a Conroe would be like, with an integrated memory controller?

Probably not that much faster than it is now; Core's advanced prefetching greatly reduces the need for low latency memory access.
Most people seem to be under the illusion that the K8's IMC is wholly responsible for the performance improvement over the K7. The fact is, AMD attributes 20% of the performance improvement to the IMC. That means 80% is down to other enhancements. In fact, I'd be willing to bet that more of its improvement is down to the changes made to its cache than the IMC.