MIPS and memory

[lockmac]

Hi. I am doing computer systems as a subject and have an exam tomorrow and just need some quick help....

Is anyone familiar with MIPS, and the SPIM simulator? If so.. is the memory address of an instruction the same as the Program Counter? Ill show an example... this is a practice question...

2. Assume that the following program fragment is in memory (the number in square brackets
is the memory address of the instruction):
[0x5a00] bne $t1,$0,end
[0x5a04] sw $1,var # var resides in address [0xa000]
[0x5a08] div $1, $2
[0x5a0c] end: addi $v0,$0,10
- 2 -
i) What is the content of PC after the execution of ?bne $t1,$0,end?, where $t1=$0?

for question i).. would the PC be the memory address of 'end'.. which is 0x5a0c?

Also.. i have a question like this:

Assume a 8MB memory. How many wires do you need in a bus if the memory is:
a. byte-addressable
b. word-addressable, and the word size is 16-bits

Question 8 (LN4)
How many address lines (bits in the address) and I/O lines (bits in the actual data) are needed for
each of the following word-addressable memories?
a. 2K x 16
b. 16K x 8
c. 4M x 12

Basically.. i dont really know how to work this out..anybody able to help me or point me in the right direction?

Thanks guys

 

[GPett]

You have to highlight his invisible text to actually see his test questions.

Oh, and I have no idea.

 

[Lord Banshee]

"memory address of an instruction the same as the Program Counter"

For MIPS yes, at least the MIPS32 i built in Comp Arch it was but i guess if it was a something unique it doesn't need to be...

i) i would say 0x5a04
bne $t1, $0, end is "branch not equal", in this case $t1 = $0 so it doe not branch

ii) Sounds like a trick question, it seems that it wants you to think of address lines, but it says "bus" so i would assume data bus. So for (a) byte = 8 bits (b) 16-bits. Maybe not so i do not know lol

iii)
a) 2K = 2*1024 = 2048 -1 = $7FF = 11 bits, This is the address
the 16 is the data size, so 16 bits.

Hopefully this helps and i explained and read the questions correctly, if not google is a nice friend. For question ii and iii is stuff i covered in digital logic so website involving memory mapping should explain this. For MIPS, there is a ton of website on MIPS

-Chris

 

[esun]

i) Agree that it's 0x5a04.

For the bus question, it is a bit vague. Consider that you need to address the RAM as well, not just access data from it. Sure, you only need 8 or 16 wires to access the data from a byte or word (respectively), but what about addressing that byte or word?

a) 8MiB = 8 * 2^20 = 2^23 bytes. If we address by bytes, then we would 23 wires to access all 2^23 bytes. You'd also need 8 for the data bus.
b) We'd need half as many wires if we addressed by words, or 22 wires. You'd need 16 for the data bus.

Question 8

a) 2K = 2^11, so 11 address, 16 data
b) 16K = 2^14, so 14 address, 16 data
c) 4M = 2^22, so 22 address, 12 data

FYI, these kinds of numbers show up in actual datasheets all the time. For example: http://inst.eecs.berkeley.edu/...uments/256MSDRAM_G.pdf

That's a datasheet for a 256MB module of Micron SDRAM. If you take a look at Table 1: Address Table, you'll see there's 3 versions: 64M x 4, 32M x 8, 16M x 16. In each case it shows you the rows, column, and bank addressing. If you add those up (those are the address bits) you'll find they, in each case, equal log_2(64M0, log_2(32M), and log_2(16M). In the General Description it talks more about the I/O being 4-bits, 8-bits, and 16-bits for each of those configurations.