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Discussion MI455X Estimation of structure etc

Where do you want to be as an HBM vendor?

  • Micron 마이크론

    Votes: 3 42.9%

  • Samsung 삼성

    Votes: 3 42.9%

  • Hynix 하닉

    Votes: 3 42.9%
  • Total voters
    7
1250

1250

Member
9122e0d1f8202dbc.jpg
In order, Bi/o(bigger), i/o(normal), MID, c-hbm
e.g. tsmc MID + Bi/o(tsmc combination)
samsung MID + i/o + c-hbm(sam combo)​
 

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base die precess update(presume)

standard hbm(S-hbm) custom hbm(C-hbm) H(skH) S, M(micron)
S-hbm4(also 4E)
H 12nm S sf4x M dram(n12)
C-hbm4(only amd)
S sf4x H,S 12nm?(It's a different b-die with the same process)
C-hbm4E
H n3p S sf2 M n3p

p.s That means AMD has to make three versions of the base die, spending hundreds of millions of dollars(memory guys claim)
 
Last edited:
1250 said:
base die precess update(presume)

standard hbm(S-hbm) custom hbm(C-hbm) H(skH) S, M(micron)
S-hbm4(also 4E)
H 12nm S sf4x M dram(tsmc?)
C-hbm4(only amd?)
S sf4x
C-hbm4E
H n3p S sf2 M n3p
Click to expand...

Are you saying that AMD may offer 2 different base dies - Standard and Custom?

BTW, who is making the custom base die?
 
memory guys (Samsung, skHynix)
Here, it's basically C-HBM4.
The memory guys are basically not interested in AMD(or strong NDA)
The consensus among official custom HBM team (probably) is that AMD isn't using C-HBM4 due to cost issues and AMD's lack of capacity.
But this time, my side has a consulting person(Maybe? for Google, Broadcom, AMD, etc. He knows the capacity of LPDDR.) on the scene
So, memory guy with the strongest argument is that the supply shortage has led to the switch to using S-HBM(claim: lpddr controller is inside the GPU. LPDDR is connected to the IOD or MID, just like a graphics card.)
p.s He's probably a planning person and has access to the MI4xx plan.
 
Last edited:
base die precess update(presume)

standard hbm(S-hbm) custom hbm(C-hbm) H(skH) S, M(micron)
S-hbm4(also 4E)
H 12nm S sf4x M dram(n12)
C-hbm4(only amd)
S sf4x H,S 12nm?(It's a different b-die with the same process)
C-hbm4E
H n3p S sf2 M n3p

p.s That means AMD has to make three versions of the base die, spending hundreds of millions of dollars(memory guys claim)
 
This custom base die stuff only makes sense if you have some type of standardization regarding interface between DRAM stacks and base die.

I would propose following:
If memory guys do not want to change their DRAM array structure etc. one solution could be an intermediate interface die placed between DRAM stacks and the base die. This intermediate interface die acts as an RDL (redistribution layer).
That would also be a solution for vendor specific base die (AMD might design it differently compared to Nvidia). But the better solution would be, that the custom base die interface to the DRAM stack is really standardized.
The memory guys might still need the RDL die but it would be the same for all custom base die versions from any chip design company.
 
That's why I know JEDEC exists.
Joe Macri (Board of Directors) is the AMD vice president known for creating HBM.
But the problem here is that memory guys claim JEDEC only sets the physical specifications, and S-HBM is no different from custom.
I've been reading some of the opinions exchanged on Twitter, so it's probably easier to understand.
There are differences of opinion.
https://twitter.com/x/status/2022696471535997035
 
1250 said:
That's why I know JEDEC exists.
Joe Macri (Board of Directors) is the AMD vice president known for creating HBM.
But the problem here is that memory guys claim JEDEC only sets the physical specifications, and S-HBM is no different from custom.
I've been reading some of the opinions exchanged on Twitter, so it's probably easier to understand.
There are differences of opinion.
https://twitter.com/x/status/2022696471535997035
Click to expand...
AMD are not exactly going to be sharing proprietary knowledge with Samsung (or SK Hynix) about custom base dies they haven't yet sent to fab, so it stands to reason that the off the shelf base die engineer isn't going to know what AMD's capabilities are yet.

I'm not even sure that there is any reason that such an engineer would have access to such information even if the Samsung fab had the masks on site - competent corporate security measures would demand proper separation of information for said fabs to keep their semicon customers trust and not incur ruinous lawsuits.
 
The person who is making the strongest claims right now is (probably) a planning person. He is confident that he has the latest and greatest information. He knows what HBM speeds companies want, etc. He also seems to have access to the MI455x planning. There is also a consulting person who works with Google, AMD, etc. He has hinted that he has developed a custom HBM, but I think it could be a PoC.

P.s memory guy's mainstream opinion
first c-hbm is nvidia c-hbm4e
 
adroc_thurston said:
Once again, this is wrong.
MI400's have kustom HBM with LPDDR shoreline stashed in each base die.
Click to expand...
Thanks
I don't know what information they have access to, and they don't seem to even know they're under an NDA. They're convinced that 4E isn't a hostile custom HBM, but they claim they have no information about 5.(parallel to them). I've tried suggesting solutions, but they're completely useless. They're brainwashed by development costs and such. AMD is a small, corner store company with insufficient capabilities. They think JEDEC is useless and that they're just making their own custom products.
 
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adroc_thurston said:
this is very very very funny (AMD R&D opex was 600m higher YoY last Q).
Click to expand...
The conversation of x above is a stereotype, they talk as if the development cost is 600m
If it costs that much, I'd rather use s-hbm. But nah
BTW, what do you think about the unit price? They believe that Nvidia is buying it for $700, and Lisa is buying it for cheap(450) with a lower clock speed. I wonder if the unit price will go up if they use a custom base die.
 
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AMD will officially announce the custom base die, right?
There was an article that said the S-HBM base die was 80%(Originally it was 90%, but after fixing performance issues) I don't know when production will start, but I hope it goes well.
 
adroc_thurston said:
this is very very very funny (AMD R&D opex was 600m higher YoY last Q).
Click to expand...
1250 said:
The conversation of x above is a stereotype, they talk as if the development cost is 600m
If it costs that much, I'd rather use s-hbm
Click to expand...
Based on adroc's reply I'd assume that this is total R&D expenditure change from 2024 Q4 -> 2025 Q4 for AMD across all silicon µArchs in various compute types (CPU, GPU, FPGA, DPU etc), hw IO (consumer and enterprise/server, including mobo chipsets) and software R&D (ROCm/HIP, gfx drivers, CPU compilers, GPUOpen academic work/collabs etc), not solely on one specific memory interface type like HBM.

It took a large amount of engineering work over multiple campuses to run a company like AMD even back when they had scaled down in the mid Bulldozer days, but these days the workload must be huge 😅
 
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