MESI state transition diagram question

[Goi]

Hi,
I was looking through the various snoopy protocols and I have a question regarding the transition from exclusive to shared state being BusRd/Flush. I understand that moving from modified to shared requires a flush from cache to memory due to the cache data being dirty, but what I don't understand is why a clean cache line in exclusive state also requires a flush to memory. It seems to me that a BusRd/- would do. Most diagrams I found on google had the extra flush, for example this one. I managed to find a diagram that agreed with me though, which is on page 30 of this powerpoint file

Could it be that the "Flush" portion of the "BusRd/Flush" action doesn't actually flush the contents of the clean cacheline to memory, but merely snoops the bus and lets the reader of the memory address(CPU2) that CPU1 had exclusive ownership of the memory address and hence letting both CPUs go into shared state rather than CPU2 going into exclusive state? Or, the Flush actually flushes the cacheline to CPU2 rather than let CPU2 fetch it from memory(assuming that CPU to CPU communication is faster than CPU to memory).

Also, I was trying to find out more information on the MOESI protocol, including state transition diagrams, but somehow all the information ended at MESI. Does anyone know of any good references for this?

Thanks!

 

[CTho9305]

By supplying the data to the bus ("flushing" may not mean removing it from your cache - e.g. flushing dirty data just writes back the dirty data but keeps it in cache), you can do a cache-to-cache transfer rather than a memory-to-cache transfer, and cache-to-cache can be faster.

 

[Goi]

Thanks. I know that flush doesn't mean evicting the cacheline. I just thought that CPU2 could just get the required cache block from memory, but I guess in most cases cache-cache transfer would be faster. I guess it's also up to the actual implementation whether to do a BusRd/Flush or just a BusRd/-?