- May 10, 2002
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I'm curious about the memory timing options available on the LP SLI-DR.
The following options can be adjusted in the A8N-SLI Deluxe BIOS (1006):
Where ranges specified, the intermediate steps are 1.
1T/2T -> duh
CAS# latency (Tcl) -> 2.0, 2.5, 3.0
RAS# to CAS# delay (Trcd) -> 2 to 7
Min RAS# active time (Tras) -> 5 to 11
Row precharge Time (Trp) -> 2 to 6
Row Cycle Time (Trc) -> 7 to 13
Row Refresh Cycle Time (Trfc) -> 9 to 15
Write Recovery Time (Twr) -> 2 to 3
Read-to-Write Delay (Trwt) -> 1 to 6
After looking at the DFI manual, it would seem there are more options available.
Row to Row Delay (Trrd)
Write to Read Delay (Twtr)
Refresh Period (Tref)
Write CAS Latency (Twcl)
I'm curious what ranges are available on the DFI for all settings.
The following options can be adjusted in the A8N-SLI Deluxe BIOS (1006):
Where ranges specified, the intermediate steps are 1.
1T/2T -> duh
CAS# latency (Tcl) -> 2.0, 2.5, 3.0
RAS# to CAS# delay (Trcd) -> 2 to 7
Min RAS# active time (Tras) -> 5 to 11
Row precharge Time (Trp) -> 2 to 6
Row Cycle Time (Trc) -> 7 to 13
Row Refresh Cycle Time (Trfc) -> 9 to 15
Write Recovery Time (Twr) -> 2 to 3
Read-to-Write Delay (Trwt) -> 1 to 6
After looking at the DFI manual, it would seem there are more options available.
Row to Row Delay (Trrd)
Write to Read Delay (Twtr)
Refresh Period (Tref)
Write CAS Latency (Twcl)
I'm curious what ranges are available on the DFI for all settings.