- Aug 25, 2001
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Did you ever happen to notice, that on current Intel 775-supporting chipset boards, the memory ratios are all multipliers, with the lowest being a 1:1 setting with the true FSB?
But on an AMD S939-supporting chipset board, the memory ratios all seem like divisors, with the highest setting being 1:1 with the FSB?
I'm just curious why this is so.
(And for a third data-point, NVidia 650i and 680i chipsets allow a totally async memory and FSB ratio, with individual frequencies for each.)
I for one, would like it if I could run slower memory speeds with a higher CPU FSB on C2D rigs, but it seems as though this simply isn't possible on Intel chipsets. Not so with AMD64, for those systems it's trivial to get a higher CPU FSB while still using slower RAM with a divisor.
It seems mostly pointless to run RAM at a faster speed than the processor's FSB anyways, although I realize that peripherals need RAM bandwidth too (AGP/PCI-E, etc.)
I should note that there is an exception, I run a C2D rig with an intel 865PE chipset, which does have memory divisors and not multipliers.
But on an AMD S939-supporting chipset board, the memory ratios all seem like divisors, with the highest setting being 1:1 with the FSB?
I'm just curious why this is so.
(And for a third data-point, NVidia 650i and 680i chipsets allow a totally async memory and FSB ratio, with individual frequencies for each.)
I for one, would like it if I could run slower memory speeds with a higher CPU FSB on C2D rigs, but it seems as though this simply isn't possible on Intel chipsets. Not so with AMD64, for those systems it's trivial to get a higher CPU FSB while still using slower RAM with a divisor.
It seems mostly pointless to run RAM at a faster speed than the processor's FSB anyways, although I realize that peripherals need RAM bandwidth too (AGP/PCI-E, etc.)
I should note that there is an exception, I run a C2D rig with an intel 865PE chipset, which does have memory divisors and not multipliers.