As far as I understand, RAM communicates with the CPU through the FSB in most systems (I've heard that is not the case in nForce chipsets). If the FSB is rated at, say, 400MHz (1600MTs effective); then the maximum speed that RAM may be clocked at is 400MHz* (800MTs effective: DDRx-800). When an enthusiast decides to overclock his CPU, unless he has an unlocked multiplier, he must increase the FSB. This puts strain on the RAM to keep up with the FSB in clock rate.
Enter the memory divider. The MD allows system RAM to run asynchronously with the FSB in a ratio described as RAM:FSB. With a MD of 1:2, for instance, RAM would be able to run at 1/2 the speed of the FSB thereby producing system stability. However, I always thought that the MD could only be configured to allow the RAM to run slower than the FSB. This would be because RAM communicates with the CPU through the FSB, so the FSB is the limit to how fast the RAM can run. But after reading numerous threads in this and other forums, I have seen users running their RAM faster than the FSB using a MD such as 5:4. Some of these users even have screenshots to back this up, so I know they didn't just reverse the MD ratio to FSB:RAM. How can the RAM, even with a MD, be able to be clocked higher than the FSB and still work properly?
*By the way, what is the difference between the I/O memory bus by which we match the FSB to, and the memory clock? I assume the I/O bus is what interfaces with the FSB, while the memory clock is what the individual memory cells run at. However, given a common memory clock such as 200MHz, the accompanying I/O bus speeds relative to DDR1/2/3 are: DDR-400, DDR2-800, and DDR3-1600. If the memory cells are running at the same speed in each case, how can increasing the I/O bus rate increase the amount of transfers? What I mean is, the memory cells hold the actual data, increasing the I/O bus would appear to me to be wasted since at maximum it "should" only be able to transfer as fast as the memory cells can feed it data.
Enter the memory divider. The MD allows system RAM to run asynchronously with the FSB in a ratio described as RAM:FSB. With a MD of 1:2, for instance, RAM would be able to run at 1/2 the speed of the FSB thereby producing system stability. However, I always thought that the MD could only be configured to allow the RAM to run slower than the FSB. This would be because RAM communicates with the CPU through the FSB, so the FSB is the limit to how fast the RAM can run. But after reading numerous threads in this and other forums, I have seen users running their RAM faster than the FSB using a MD such as 5:4. Some of these users even have screenshots to back this up, so I know they didn't just reverse the MD ratio to FSB:RAM. How can the RAM, even with a MD, be able to be clocked higher than the FSB and still work properly?
*By the way, what is the difference between the I/O memory bus by which we match the FSB to, and the memory clock? I assume the I/O bus is what interfaces with the FSB, while the memory clock is what the individual memory cells run at. However, given a common memory clock such as 200MHz, the accompanying I/O bus speeds relative to DDR1/2/3 are: DDR-400, DDR2-800, and DDR3-1600. If the memory cells are running at the same speed in each case, how can increasing the I/O bus rate increase the amount of transfers? What I mean is, the memory cells hold the actual data, increasing the I/O bus would appear to me to be wasted since at maximum it "should" only be able to transfer as fast as the memory cells can feed it data.
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