Mem Latencies

[b4u]

Hi,

I recently saw an article which explained about the various DRAM timings, and I have a few questions:

[1] I have tRCD(ras-to-ras delay), tCL(cas latency), tRAS(row active time), tRP(ras precharge time). Now I have a memory module with settings 2-2-2-6-T1. Which ones are which?

[2] Many DDR RAM chips are subdivided into four segments (banks). If I configure my system to access the 4 banks interleaved, I can gain some performance. How can I say if a memory module has 4 banks?


Thanks

 

[Peter]

(2) All SDRAM chips 64-Mbit capacity and higher are four-bank. No need to worry about that.

(1) tRAS is the large value in there. Normally tCL is the first value given, as it has the largest impact. tRCD and tRP are the other "2" values in there, I don't know which is which, and this isn't of much importance either. The "T1" behind it all is not something standard.

 

[Arcanedeath]

The T1 is the command rate, just an FYI

 

[b4u]

Thanks for the replies

So it should be something like:

tCL-tRCD-tRP-tRAS-CommandRate

anyone can confirm the order?

Also what does the Command Rate means? What impact does it have?

 

[capybara]

there is no industry standard order. the order is whatever is listed in your bios.
I have seen this:
active pre-charge 6
ras 3
ras to cas 3
cas 2
pretty commonly in amds,
i think the order for intels maybe commonly different, imho

 

[b4u]

Another question, this time a more specific one:

Assuming 2 identical configurations, 1Gb (2x512Mb) Running Dual. One running with settings 2-2-2-6-T1, the other running 2-3-3-7-T1.

Is the difference noticeable?

 

[Smilin]

It will be a minimal improvement to the naked eye - on benchmarks the difference will be very clear. Once your processor has reached the 'expensive' speeds of say 2.8ghz or higher putting faster memory in will be much more cost effective for added performance.

 

[Maddscientist]

2.2.2.5 for DDR2700 TO 3700 is supposed to be the sweet spot.


Auto config should be Off

Bank Interleaving Should Be 4

Burst Length should be 8

Cas Latency Should be 1.5 or 2.0

Command Rate Cmd should be 1

Ras Precharge Delay Should be 2

Ras-Cas delay should be 2

Row active time should be 5 or 4 |5 recommended

This is a ddr crash course these timings are the most recommended timings for new 865PE/875P||Nforce2 boards. If your ram can hit these timings you should Have the ultimate middle ground in high performance for DDR while not sacraficing stability.

 

[Amorphus]

some memory company (think it was GeIL, or something) recommends (t)RAS to be (t)CL+(t)RP+2, because it gives the memory time to acess, otherwise the computer stops acess while the memory is still processing. like your parents closing a book in your face before you're finished with it. so in theory, 2-2-2-6 would perform better than 2-2-2-5. and in fact, if I weren't so lazy, I would dig up a thread on amdmb.com that was discussing this, that higher RAS timings would actually increase performance somewhat, because it reduced the amount of re-computation the controller had to do. in fact, the "sweet spot" turned out to be around 10 (11, actually, but it may not be the same for you).