manufacturing process a random number?

[sash1]

How do they come up with the next fabrication process? Is it just an arbitrary number or is it a specific predermined number?

Thanks,

~Aunix

 

[Eskimo]

Historically each subsequent node is 0.7x that of the previous generation. For example 180nm*0.7 = 126nm which was rounded off to be 130nm (.13um). Traditionally the driver of new manufacturing processes has been the DRAM half-pitch requirements. Modern MPU (microprocessor unit) gate lengths are much shorter than even the DRAM half-pitch however and represent the smallest single feature produced today. Therefore modern roadmaps address both the DRAM and MPU dimensions. The industry has a standard roadmap by which they plan future products and processes. You can read this roadmap in it's entirety at the public ITRS website.

The ITRS (international technology roadmap for semiconductors) is comprised of a consortium of chip makers, tool vendors, and educational/government research institutions.

 

[sash1]

"Historically each subsequent node is 0.7x that of the previous generation. For example 180nm*0.7 = 126nm which was rounded off to be 130nm (.13um)."

Wow, weird how that works. Is that just a mathematic coincidence... I doubt AMD says, "for our next manufacturing process, multiply 180nm by .7 and that will be what we use!"

Thanks for the link... 194 pages? gah, mebbe I'll browse through.

Is there some technological reasoning behind why they don't use .12, .11 or .10?

Thanks,

~Aunix

 

[Eskimo]

There are some companies, usually DRAM that produce products on odd or "half-node" processes. Such as .11um, .14um, and earlier .15um. It's a balance between technological and business issues. Each company has to evaluate for themselves whether it is worth the time and money needed to move to a .11um process when if they waited just a little longer they could move to .09 (90nm) and realize perhaps even greater benefits.

It's a complex decision that has to do with the toolset a fab is equipped for. Perhaps a fab designed for .18um could push their tools to .11 but not 90nm which is entirely possible. For example using phase shift mask technology it has been shown you can extend 248nm DUV scanners to print .11um features. But at 90nm you lose nearly all your process latitude with 248nm and most companies are finding it necessary to try to implement 193nm lithography at that node. Another example is that at the 90nm node many high performance CMOS manufacturers are attempting to integrate low k dielectric materials into their interconnect stacks to lower the RC delay overhead and allow faster operation. Since DRAM is really not limited by RC overhead at all they would rather move immediately towards say .11um to realize the savings in silicon area consumed per Mbit.

Rather than read the entire document if you confine yourself to the forward I think you'll find many of the answers you seek. The 0.7x factor has simply been a convenient factor that allows MPU manufacturers to keep up with 'Moore's Law'.

 

[sash1]

Thank you Eskimo!

I think I will check out the forward, if it seems interesting mebbe some more, but 194 pages is a bit much!