Mainstream Intel Core Processors will not support AVX 512 from Skylake – Only Xeon

[SAAA]

...
You can make larger caches that have low latency however -- IBM's Power8 has a 64KB L1D with a 3-cycle latency, compared to Intel's 32 KB L1D with a 4-cycle latency -- the tradeoff being that Power8's L1D consumes an inordinate amount of power.

Every time I hear of Power8 I learn something new and extraordinary, is that L1 really so good?!
I wish that chip was released for common desktops too, just a 2-3 core variant would be soo great to fiddle with... and I won't care of x86 compatibility for once, just let me bench it in some distro for the lols!

 

[III-V]

If by skylake-s you mean skylake server then yes. If by s you mean socketed then nope.

Skylake-S is the name for the desktop version (it might stand for socketed, come to think of it). Skylake-S includes Xeon, as well as Core iX -- and yeah, Core iX is not getting it (apparently according to Intel itself), which I imagine is what he was claiming.

Every time I hear of Power8 I learn something new and extraordinary, is that L1 really so good?!
I wish that chip was released for common desktops too, just a 2-3 core variant would be soo great to fiddle with... and I won't care of x86 compatibility for once, just let me bench it in some distro for the lols!

It has a 3-cycle latency, yeah (minimum, varies by operation of course):

Fixed-point loads have a three-cycle load-to-use latency
on a L1 D-cache hit.

I cannot find the RWT thread that has the power consumption information, though -- I don't think google's bots crawl through there, so I am having to look the hard way. The number was astonishingly high, from what I can remember.

Supposedly Intel only lost 3 or 4% performance regressing from 3 to 4 cycles, according to Anand's Nehalem bits.

 

[mikk]

Skylake-S is the name for the desktop version (it might stand for socketed, come to think of it). Skylake-S includes Xeon, as well as Core iX -- and yeah, Core iX is not getting it

Keep in mind that Xeon E3 is unlikely too.

We had committed that Intel® AVX-512 would also be supported by some future Intel® Xeon® processors scheduled to be introduced after Knights Landing.

That implies SKL-EP/EX which are indeed scheduled after Kinghts Landing.

 

[III-V]

Keep in mind that Xeon E3 is unlikely too.

That implies SKL-EP/EX which are indeed scheduled after Kinghts Landing.

Interesting, and probably a good decision on their part. Expanding the vector units to 512-bits would be worthless for 99% of their end users, and would take up a fair bit of space. The 1% that do care would likely be using the EP/EX variants anyway. Or, the 1% that care and actually would make use of it.

That'd be the first time, as far as I know, that EP/EX would get a meaningfully-different core floorplan (excluding L3).

AVX-256 has basically only been good for creating overly-conservative max stable frequencies under linpack