looking for a tool to generate block diagram from verilog files

[Special K]

Is there a tool that will take a structural verilog file as input, and output a block diagram of the system represented by the verilog file, with labeled modules, ports, nets, etc? This is probably a long shot, but I have a CPU that I designed for a class and just in case I have to use it later, I want to have some schematics to reference. The only problem is all I currently have is a bunch of hand drawn ones in pencil that are already quite smeared.

 

[shortylickens]

Well, I wont lie to you. I have no idea what a verilog file is, but I do know about block diagrams. I cant think of any programs that will auto generate one based on an external input, but if you made the effort to do it once by pencil it may be worth your time to do it once more in a program and save it.

http://www.smartdraw.com/specials/diagram.asp?type=10480&id=10480
http://www.ptc.com/company/mail/express200204/rsd.htm
http://www.diagramstudio.com/schematic_diagram_software.htm
http://www.elecdes.com/elecdes.htm

Just about anything that can do schematics can also do block diagrams.

Or you can use Microsoft Paint. I did it for a comm systems class. But that was a one time thing and next time I intend to use the proper software.