Question List of DRAM-less SSD controllers?

[cbn]

Looking at number of P/E cycles the MX500 and the 545s however; then they are both specced for 1500 P/E cycles.

Difference in Wear Level factor?

Difference in Write Amplification factor?

 

[IntelUser2000]

Difference in Wear Level factor?

Difference in Write Amplification factor?

This is why.

upgraded error correction and end to end data path protection it offers

It should be quite obvious why. As the NAND media degrades with usage, the voltage levels become rough. The one with the better error correction can go without errors for a longer time than one without. Therefore, the upgraded ECC version can be rated for higher life cycles.

If you simply do 500GB x 1500 cycles, then the theoretical maximum write cycles turn out to be 750TB. Both are significantly under this, because wear levelling isn't perfect, and real world usage can easily overwhelm algorithms.

Few things work to mitigate the limited write cycle issue for NAND:
-DRAM buffers
-Wear levelling algorithms
-Error correction
-Overprovisioning

 

[cbn]

What is confusing to me is that despite the Intel 545s having more ECC (via SM2259) it has the same P/E rating as the MX500.

This implies the Intel SSD would be using lesser grade IMFT NAND and making up for it with a better controller.

 

[VirtualLarry]

What is confusing to me is that despite the Intel 545s having more ECC (via SM2259) it has the same P/E rating as the MX500.

This implies the Intel SSD would be using lesser grade IMFT NAND and making up for it with a better controller.

I thought that the P/E rating was wholly dependent on the NAND grade / technology / process, and not the controller? The TBW of a drive, being a factor of the P/E, the controller, ecc, and NAND grade altogether, including firmware tweaks to one mfg's drive over another? (For example, slowing writes down in "enterprise" versions of drives, to enhance endurance.)

 

[cbn]

I thought that the P/E rating was wholly dependent on the NAND grade / technology / process, and not the controller? The TBW of a drive, being a factor of the P/E, the controller, ecc, and NAND grade altogether, including firmware tweaks to one mfg's drive over another? (For example, slowing writes down in "enterprise" versions of drives, to enhance endurance.)

Here is what Tom's SM2256 article said about Silicon Motion's then new NANDXtend ECC:

https://www.tomshardware.com/reviews/silicon-motion-sm2256-ssd-preview,4066.html

ilicon Motion's internal testing with a 120-degree bake to accelerate the degradation process shows a 3x endurance increase.

The end result is that SSD vendors can use lower-cost, lower-endurance flash and still guarantee the same number of writes per day that we have now.

And looking at the following formula I don't see an input for ECC level:

(The ECC looks built into the P/E cycles*)

*Greater ECC with "X" type of NAND = Increased P/E vs. Lower ECC with "X" type of NAND = Decreased P/E

 

[IntelUser2000]

ECC can be in individual NAND chips, or be in the controller. The paragraph about the controllers used in Intel and the Crucial drive is pointing to ECC being in the controller. Of course the chip used in the Intel drive is higher end so it probably has better algorithms and bigger buffers.

That formula is probably a simple one. You can include effects of temperature, different voltages applied to the chips, and overprovisioning too.

We don't know the all the details between the drives and the controllers used and there are so many variables that can be adjusted. I admit my assurance due to being solely due to ECC was a hasty conclusion.

 

[Glaring_Mistake]

Difference in Wear Level factor?

Difference in Write Amplification factor?

I tend to be hesitant to argue for differences in TBW meaning they have different endurance but if that is the case here then I think that this would be the most likely reason because seeing as the Intel 545s has a small static SLC-cache while the Crucial MX500 has a larger dynamic SLC-cache they may behave a bit differently.
Thing is that with the MX500 you have Host Program Sectors Count (which is everything you actively tell it to write, basically ) and then you have FTL Program Page Count (which is the data that is written in the background and/or wear added by WAf).
According to documents from Micron about how to calculate WAf you should combine Host Program Sectors Count and FTL Program Page Count and then divide that with Host Program Sectors Count but the WAf you arrive at using that method can be quite different from what you get using the usual method of dividing wear as number of P/E cycles by number of Host Writes.
It may be that those documents are outdated seeing as it was written when their drives used MLC NAND with no SLC-cache.