LGA 2011 Owners.. The Xeon 8 Core 16 HT E5-2687W is finally here

[denev2004]

Yes, but that's only true for today's games.

A few years ago people were asking whether it's better to get a high clocked Core 2 Duo or a Core i7-920. At that time the Core 2 Duo ran every contemporary game just as smoothly as the Nehalem i7. But nowadays there's an advantage to having a quad-core, and it will last quite a bit longer than the dual-core.

That said, I think a 600$ i7-3930K can perhaps be justified if you need a future-proof system, but 2100$ for marginally higher peak performance is silly unless you absolutely need the added reliability of a Xeon.

Note that as the number of cores increases, the efficiency goes down because the cores have more siblings to divide their tasks between. You'll have to wait for the Haswell processors before they'll combat this with hardware transactional memory. Haswell's AVX2 support will also be quite revolutionary for PC gaming...

Actually there's something I'm wondering about...It seems that E5-2687W is only design for workstation beacuse it has a sign W. Also never had I seen servers using chips like W5580. Does that means there's a difference of reliability between the W chip and the non-W chip, or it's just the W series is a bit hot for high-density server?

 

[denev2004]

Why? What's the big deal with AVX2? (This is genuine curiosity -- I heard that AVX would be huge, but it's done nothing so far)

FMA3(although, not really a part of AVX2, but for Intel's desktop CPU part, it will first come out with Haswell & AVX2), Gather/scatter support and widen vector-INT instruction are all of great importance.
But you're right, AVX hasn't done much so far, maybe we need to wait for quite a long time to see games support these better.

 

[denev2004]

Id rather have a 64 thread AMD 6262 , or a 32 thread AMD 6282 SE rig for the same price ^^

I'd like to say Interlagos chips really looks cool, just imagine how much blocks can I see in the task manager....
And AMD's sever chips also has a better performance pre price these days. Although there were once better at absolute performance. Before Intel released Nehalem-EP

 

[Don Karnage]

Hey, when you get the chip, could you start a thread and give us some benchies? In specific, I'd love to see some cache and memory bandwidth benchies...

Plan on it. Can't wait to run some multithreaded benchmarks

Bold move :thumbsup:

Please advise on oc experience, headroom and temps! Is this going to work out of the box with the current R4E BIOS do you think ?

I've ran an Xeon 8 Core ES on this board without issue so i don't think the 2687W will be a problem either.

 

[Arachnotronic]

I just hope bclk straps work on the E5-2687W!

 

[CPUarchitect]

Why? What's the big deal with AVX2? (This is genuine curiosity -- I heard that AVX would be huge, but it's done nothing so far)

The big deal with AVX2 is that it offers a vector equivalent of every scalar instruction. And this is the principle that makes GPUs so fast. It allows any code loop with independent iterations to run in an SPMD fashion. So with AVX2 a fair bit of code could run up to 8 times faster.

AVX1 didn't make much of an impact because it widened only the floating-point instructions to 256-bit. Doubling the theoretical floating-point performance looked good on paper but this extension is very awkward to use when you need to mix in a few integer operations. It requires processing the upper and lower 128-bit separately and using additional instructions to transfer the data to and from the upper part of the vector register. Furthermore, Sandy Bridge doesn't increase the cache bandwidth so AVX1 code is often starved for data. But it set the stage for AVX2 by introducing the VEX encoding format, widening the registers, using two execution stacks, etc. Basically AVX2 was too big to implement all at once so they had to make a compromise and this became AVX1. So the announcement of AVX was pretty huge in the sense that Intel made the bold move to widen the SIMD instructions, although it quickly became clear that the first version would lack some vital pieces.

Thankfully Haswell will fix all the shortcomings of Sandy Bridge at once. The integer vector instructions are widened to 256-bit (meaning a single instruction can do what you previously needed 3-4 for), it will bring the long-awaited gather support (allowing to load up to 8 data elements in parallel instead of sequentially), it will add vector-vector shifts (a relatively simple instruction that nonetheless has been lacking from the SIMD instruction set for 10 years), it doubles the theoretical floating-point performance again with FMA, and it will inevitably double the cache bandwidth.

 

[Edrick]

Thankfully Haswell will fix all the shortcomings of Sandy Bridge at once. The integer vector instructions are widened to 256-bit (meaning a single instruction can do what you previously needed 3-4 for), it will bring the long-awaited gather support (allowing to load up to 8 data elements in parallel instead of sequentially), it will add vector-vector shifts (a relatively simple instruction that nonetheless has been lacking from the SIMD instruction set for 10 years), it doubles the theoretical floating-point performance again with FMA, and it will inevitably double the cache bandwidth.

Hence my excitement!!!!

Thank you CPUarchitect, very nice description.

 

[CPUarchitect]

The proper comparison would be between a C2D and a C2Q (there are no IPC gains).

Actually Nehalem was a mixed bag because it had an integrated memory controller while the 8 MB L3 cache was much slower than Penryn's 6 MB L2 cache. Also the bypass delays were higher in Nehalem. But most of all the i7-920 clocked at 2.66 GHz / 130 TDP while the Core 2 Duo clocked higher and was easier to overclock further due to a much lower TDP. So for the games at that time (which were mostly single-threaded) the Core 2 Duo was in fact slightly faster. And the cheaper motherboards made it look like quite an attractive deal. But my point is that the Core i7 was a much better long-term investment since it will outperform the Core 2 Duo for today's games, which are often multi-threaded.

So when TakeNoPrisoners suggested getting an i5-2500K because it's great for running today's games, I had to point out that the same kind of logic has been used to decide between the Core 2 Duo and Nehalem and didn't lead to the best purchase.

And the fact is, if you need an upgrade over a C2D in gaming, 95% of the time you need an upgrade over a C2Q. A C2Q will not have "future proofed" you.

Which is exactly why I'm talking about people who tried to decide between a Core 2 Duo and Core i7-920 instead.

 

[Arachnotronic]

The big deal with AVX2 is that it offers a vector equivalent of every scalar instruction. And this is the principle that makes GPUs so fast. It allows any code loop with independent iterations to run in an SPMD fashion. So with AVX2 a fair bit of code could run up to 8 times faster.

AVX1 didn't make much of an impact because it widened only the floating-point instructions to 256-bit. Doubling the theoretical floating-point performance looked good on paper but this extension is very awkward to use when you need to mix in a few integer operations. It requires processing the upper and lower 128-bit separately and using additional instructions to transfer the data to and from the upper part of the vector register. Furthermore, Sandy Bridge doesn't increase the cache bandwidth so AVX1 code is often starved for data. But it set the stage for AVX2 by introducing the VEX encoding format, widening the registers, using two execution stacks, etc. Basically AVX2 was too big to implement all at once so they had to make a compromise and this became AVX1. So the announcement of AVX was pretty huge in the sense that Intel made the bold move to widen the SIMD instructions, although it quickly became clear that the first version would lack some vital pieces.

Thankfully Haswell will fix all the shortcomings of Sandy Bridge at once. The integer vector instructions are widened to 256-bit (meaning a single instruction can do what you previously needed 3-4 for), it will bring the long-awaited gather support (allowing to load up to 8 data elements in parallel instead of sequentially), it will add vector-vector shifts (a relatively simple instruction that nonetheless has been lacking from the SIMD instruction set for 10 years), it doubles the theoretical floating-point performance again with FMA, and it will inevitably double the cache bandwidth.

So Haswell will be a substantially more advanced CPU than SNB? Do you think the move from SNB -> HSW will be more substantial than the move from NHM -> SNB?

 

[CPUarchitect]

So Haswell will be a substantially more advanced CPU than SNB? Do you think the move from SNB -> HSW will be more substantial than the move from NHM -> SNB?

I'd love to make that a univocal "yes", but to be completely fair it depends on your perspective. Sandy Bridge has a radically new front-end, physical register files which had a big impact on the out-of-order execution logic, laid out the groundworks for AVX and all its future extensions, and has very advanced power saving and turbo clocking features. Not to mention a fully integrated GPU and QuickSync. So it's a massive advancement from a technological point of view, but despite that it's not substantially faster than Nehalem on a clock-for-clock basis.

From the same technological point of view, Haswell isn't exactly a huge step up. AVX2 doesn't require a whole lot of extra hardware. The VEX decoders are already in place and the 256-bit registers and data busses are already there! All they need to do is make the floating-point execution stack capable of integer operations, in very much the same way Sandy Bridge made the integer execution stack capable of floating-point operations for AVX1. And doubling the cache bus widths won't exactly be hard on a 22 nm process. But in contrast to Sandy Bridge these relatively straightforward changes could have a big impact on real-world performance.

Of course gather support and transactional memory aren't exactly trivial features, and Intel claims a 20x improvement in standby power consumption which is also very impressive. So overall they probably have an equal amount of engineering effort put into them. It's just that Haswell will be more impressive from the consumer's perspective.

 

[blckgrffn]

Intel has had 8 core/16 thread x86 chips available for over 2 years, and 10 core/20 thread processors available for nearly a year.

Being ignorant to a product line is not an excuse for making things up to support your bizzare views.

First off, I've read the entire thread, so yeah, I know where this went.

But to this: show me those chips that I could install in an ATX motherboard under my desk though. -EX chips don't count for anyone buying consumer class hardware.

I am very much not ignorant of these chips but I got the joke.

I mean, Power7 is pretty epic and all that, but we don't even mention that here - as if they don't exist. For nearly everyone here they are novelties to be mentioned in extremely specific cases. It's arguably in the same class as the -EX line from Intel.

Heck, AMD is so much more approachable from the Opteron standpoint in that anyone of us here could have 16 "core" CPU if we wanted... there just isn't an Opteron "EX". Consider that yet another segment surrendered by AMD to Intel.

On topic - awesome. I hope that they get cheaper fast, though. Ideally, they'd push down the hexacore chip prices.

 

[Arachnotronic]

I'd love to make that a univocal "yes", but to be completely fair it depends on your perspective. Sandy Bridge has a radically new front-end, physical register files which had a big impact on the out-of-order execution logic, laid out the groundworks for AVX and all its future extensions, and has very advanced power saving and turbo clocking features. Not to mention a fully integrated GPU and QuickSync. So it's a massive advancement from a technological point of view, but despite that it's not substantially faster than Nehalem on a clock-for-clock basis.

From the same technological point of view, Haswell isn't exactly a huge step up. AVX2 doesn't require a whole lot of extra hardware. The VEX decoders are already in place and the 256-bit registers and data busses are already there! All they need to do is make the floating-point execution stack capable of integer operations, in very much the same way Sandy Bridge made the integer execution stack capable of floating-point operations for AVX1. And doubling the cache bus widths won't exactly be hard on a 22 nm process. But in contrast to Sandy Bridge these relatively straightforward changes could have a big impact on real-world performance.

Of course gather support and transactional memory aren't exactly trivial features, and Intel claims a 20x improvement in standby power consumption which is also very impressive. So overall they probably have an equal amount of engineering effort put into them. It's just that Haswell will be more impressive from the consumer's perspective.

It's when I see posts like this, that I wish the high end socket version of Haswell wasn't going to come out >1yr after the mainstream one...there's just no way I could ever justify going from a 6 core to a 4 core, even if the 4C has more sophisticated cores...

 

[NTMBK]

It's when I see posts like this, that I wish the high end socket version of Haswell wasn't going to come out >1yr after the mainstream one...there's just no way I could ever justify going from a 6 core to a 4 core, even if the 4C has more sophisticated cores...

Seriously? Would you refuse to go from a Phenom X6 to an i7-2600k? If you care more about the number of cores (or for that matter the number of MHz) than the real world performance you get from your chip, then you're a fool.

 

[Edrick]

Seriously? Would you refuse to go from a Phenom X6 to an i7-2600k? If you care more about the number of cores (or for that matter the number of MHz) than the real world performance you get from your chip, then you're a fool.

+1

I would give up 6 Westmere cores for 4 Haswell cores in a second.

 

[blckgrffn]

+1

I would give up 6 Westmere cores for 4 Haswell cores in a second.

I wish I had six westmere cores to give!

 

[exar333]

This is what makes the LGA2011 platform great; there is always an option to drop-in Xeon SKUs that may not have a consumer equivalent. Obviously not always cheap, but you can keep your SLI/XF and all the consumer goodies while getting the top of the line CPUs.

 

[IntelUser2000]

AVX IS being used though, just not in the way we were expecting. The HPC market can probably use it well too, and that will happen when the Xeon E5 arrives.

As for Haswell, the major gains are likely going to be in the Ultrabook segment again. For example, 20x reduction in standby power is exclusively Ultrabooks. Other segments will benefit, just not as much, or cares as much.

We'll probably see another ~15% IPC gain over Ivy Bridge, with further focus on low power, just like Sandy Bridge.

 

[Arachnotronic]

+1

I would give up 6 Westmere cores for 4 Haswell cores in a second.

Luckily, the resale value of this chip when the time comes will allow me to do just that

Although what I really want is a 12C/24T HSW.

 

[BenchPress]

AVX IS being used though, just not in the way we were expecting.

How? Don't leave us guessing what you think!

We'll probably see another ~15% IPC gain over Ivy Bridge...

How? IPC has only improved by single digit percentages in the last several generations, with most performance coming from higher clocks. There's little room left for improving IPC without hurting power consumption. So what technology do you expect will yield 15% ?

 

[Arachnotronic]

How? Don't leave us guessing what you think!

How? IPC has only improved by single digit percentages in the last several generations, with most performance coming from higher clocks. There's little room left for improving IPC without hurting power consumption. So what technology do you expect will yield 15% ?

SNB had a 10-15% IPC improvement over NHM without all the AVX crap. I suspect HSW will give us another 10-15% IPC on "real" code, then we'll see crazy theoretical numbers, assuming Intel doesn't starve HSW's execution units of bandwidth/resources.

 

[IntelUser2000]

How? IPC has only improved by single digit percentages in the last several generations, with most performance coming from higher clocks. There's little room left for improving IPC without hurting power consumption. So what technology do you expect will yield 15% ?

Sandy Bridge is 12-15% faster than Lynnfield: http://www.computerbase.de/artikel/prozessoren/2011/test-intel-sandy-bridge/47/

http://www.tomshardware.com/reviews/processor-architecture-benchmark,2974-15.html

How? Don't leave us guessing what you think!

You'll likely never get to see it in person beyond synthetic benchmarks like Sandra and LinX, but its used outside of the consumer market. And HPC will definitely gobble it up when Xeon E5 launches.

 

[Edrick]

I suspect HSW will give us another 10-15% IPC on "real" code, then we'll see crazy theoretical numbers

When you say "real" code, I assume you mean code not optimized for Haswell's new instructions? At that time the term "legacy" code may be a better fit.

 

[Arachnotronic]

When you say "real" code, I assume you mean code not optimized for Haswell's new instructions? At that time the term "legacy" code may be a better fit.

Hehe, fair enough. I think the perf/watt push on Intel's part is great, but they need to remember to give the CPU enough watts...and not, you know, let the GPU have the whole budget.

 

[Smartazz]

SNB had a 10-15% IPC improvement over NHM without all the AVX crap. I suspect HSW will give us another 10-15% IPC on "real" code, then we'll see crazy theoretical numbers, assuming Intel doesn't starve HSW's execution units of bandwidth/resources.

Doesn't it always take a bit of time for a new instruction set to get adopted, then those gains are realized. It wouldn't surprise me to see AVX become more common seeing as countless other instruction sets took time to adopt.

 

[Don Karnage]

Spoke to a customer service rep yesterday and the chips are incoming this week. I should have mine by friday or monday.