Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[Exist50]

Could Nvidia use Intel 4 for a 4000 Super generation? It's roughly the same density as N4 HD at 125mTr vs 123 mTr.

Intel 4 would not be equivalent from a density perspective when you factor in SRAM etc. Hell, I'd question the logic density as well. PnP is probably also worse at GPU voltages.

Apparently AMD wants to hit the ground running with TSMC's N2 (extra AMD customizations/input incoming as well?):

AMD CEO, Dr. Lisa Su, To Visit TSMC Next Month To Discuss Future 2nm, 3nm Chip Projects

AMD CEO Dr. Lisa Su and various C-level executives from the company will be visiting TSMC by next month to discuss 2nm & 3nm chip projects.

www.google.com

(source seems legit)

The topic of discussion is pure speculation. While N2 supply is certainly a possibility, doesn't seem like there're any meaningful conclusions to draw from such limited information. But realistically, N2 would be for 2026 products at best, and quite likely 2027 or even beyond. They have plenty of time to work out details.

 

[RTX]

Q&A with SiFive SVP Jack Kang: 5 nm chips with SiFive cores likely to be used in cars by 2025-2026

SiFive successfully rolled out a portfolio of automotive CPUs based on the RISC-V standard, and is about to create a new ecosystem of chips, tier-1 auto component providers and OEM partners. DIGITIMES had an exclusive interview with SiFive SVP Jack Kang, who shared what triggered the RISC-V...

www.digitimes.com

Q: Intel has this collaboration with you and also with the RISC-V community. The foundry service for all those chips will go to Intel? Or other foundry makers also have a chance.
Intel has certainly been a big proponent for RISC-V, which is great for the ecosystem. They see that this is where a lot of new chip designs are going to happen, and RISC-V will drive value for their foundry. You're going to see this across the board, all foundries are going to benefit from more RISC-V designs. This is where the foundries get to differentiate on their capabilities and features. We'll see how they compete, but it's clear that RISC-V is going to create more opportunities for all the foundries.

Is Intel even offering that node through their foundry service? And can they drive the volumes that nVidia would need while also producing enough Meteor Lake tiles?

Can Intel fab dGPU dice that large on Intel 4?

It seems like they only have RISC-V products at the moment but perhaps they could branch out to other stuff later.

 

[IntelUser2000]

Does Intel 4 have enough libraries to support a GPU? They limited the scope too much on that process. Intel 3 on the other hand is a different story.

 

[Exist50]

Does Intel 4 have enough libraries to support a GPU? The limited the scope too much on that process. Intel 3 on the other hand is a different story.

I doubt Intel 3 will be a desirable process for GPUs either. Maybe by 18A they'll have a node worth using.

 

[Saylick]

I doubt Intel 3 will be a desirable process for GPUs either. Maybe by 18A they'll have a node worth using.

Even if I3 were desirable, Nvidia would never make their high margin HPC GPUs on it simply because Intel doesn't have the track record to execute on schedule. It's just too much risk for Nvidia. If they go all out and commit a 100 series sever die to Intel and they are a year late, that means potentially a competitor catching up. If an Intel node were used, I bet it would be on something small and more or less frivolous. A pipe cleaner product.

 

[Exist50]

Even if I3 were desirable, Nvidia would never make their high margin HPC GPUs on it simply because Intel doesn't have the track record to execute on schedule. It's just too much risk for Nvidia. If they go all out and commit a 100 series sever die to Intel and they are a year late, that means potentially a competitor catching up. If an Intel node were used, I bet it would be on something small and more or less frivolous. A pipe cleaner product.

I could see Nvidia using an iterative node like 18A once 20A is proven, even if it's not quite leading edge by that point. It's what they did with Amphere on Samsung 8nm, after all. Or given that it's Nvidia, they could even dual source. For the right wafer price, they could probably be convinced.

 

[DrMrLordX]

It seems like they only have RISC-V products at the moment but perhaps they could branch out to other stuff later.

That arrangement was mildly confusing, since only one company (SiFive) was taking advantage of it. And most of the posting I'd seen indicated that the IFS 2.0 nodes would be 22FFL, Intel 3, and Intel 18a.

 

[IntelUser2000]

That arrangement was mildly confusing, since only one company (SiFive) was taking advantage of it. And most of the posting I'd seen indicated that the IFS 2.0 nodes would be 22FFL, Intel 3, and Intel 18a.

No, I think there's a much bigger design win on Intel 4. Cisco's networking switches might be on it. Back then Intel said "Custom ASIC Networking".

@Exist50 It will be leading edge if 20A and 18A comes out per their schedule.

 

[Exist50]

No, I think there's a much bigger design win on Intel 4. Cisco's networking switches might be on it. Back then Intel said "Custom ASIC Networking".

Wait a second. What were Intel's exact words? Was this ASIC chip specifically described as an IFS win?

@Exist50 It will be leading edge if 20A and 18A comes out per their schedule.

I meant that Nvidia could use it some time after it's nominally high volume ready.

 

[RTX]

https://images.anandtech.com/doci/17439/2022-06-09%2013_12_38.jpg

TSMC Unveils N4X Node: Extreme High-Performance at High Voltages

www.anandtech.com

Zen4 = N5HPC ( N5X with the new naming? )
Zen5 = N4X ( 2023 )?

Could AMD end up using 3 variants of 3nm as N3E ( 2024 ) -> N3P ( 2025 ) -> N3X ( 2026 )?
That'd be 5 generations on a single socket for an early adopter.

 

[IntelUser2000]

Wait a second. What were Intel's exact words? Was this ASIC chip specifically described as an IFS win?

You know Cisco CEO said they are one of Intel's "early foundry" customers and will use to create high end networking silicon?

Actually they haven't said it exactly. Intel's presentation just said "Custom ASIC Networking".

Also for those who don't know, Amazon's Intel deal is about using EMIB.

I doubt Intel 3 will be a desirable process for GPUs either. Maybe by 18A they'll have a node worth using.

Yea you are probably right. Just saying a minimum viable node would be 3 not 4.

 

[Exist50]

You know Cisco CEO said they are one of Intel's "early foundry" customers and will use to create high end networking silicon?

Do you have a source for Cisco being an IFS customer? I don't recall any such statement, nor can I find one with a cursory Google search.

If Intel 4 is used for a 5G networking ASIC, I'd have to assume it's from Intel's own networking team. And in many ways, that'd make sense. It was they who pulled off the first 10nm server chip, and supposedly many from that team were "borrowed" for Granite Rapids as well.

 

[IntelUser2000]

Do you have a source for Cisco being an IFS customer? I don't recall any such statement, nor can I find one with a cursory Google search.

If Intel 4 is used for a 5G networking ASIC, I'd have to assume it's from Intel's own networking team. And in many ways, that'd make sense. It was they who pulled off the first 10nm server chip, and supposedly many from that team were "borrowed" for Granite Rapids as well.

It's from Semianalysis. The custom part is an interesting statement if it's made internally. The word naturally leads into Intel IP but configured in a way desirable to the customer.

Another note: Intel claims 2x density gains on the 4 process. Yes Meteorlake doesn't achieve that but maybe it's possible and we'll see that fully realized on certain products on the Intel 3 process.

Case in point: 2.7x density of 14nm over 22nm. In what product did the density claim materialize? Remember they were going after the mobile market, or at least claiming to(who knows with BK's BS).

Atom. Airmont achieved a 64% reduction in die area over Silvemont. That's 2.77x.

What about the Iris Xe iGPU achieving nearly twice the performance over Icelake's GPU despite being on the same process node with 50% more execution resources? They also claimed big gains with 10nm over 14nm.

Maybe in the same way it's possible, but we won't see for all. Clearly for the core lineup(or Core lineup lol!) the reduction in size was a steady 50% as long as there was such thing as process technology.

 

[DrMrLordX]

No, I think there's a much bigger design win on Intel 4. Cisco's networking switches might be on it. Back then Intel said "Custom ASIC Networking".

Hmm hadn't heard that. Interesting. Didn't think they'd be pushing much of anything on Intel 4 via IFS 2.0.

 

[Exist50]

It's from Semianalysis.

Then I'm pretty sure it simply doesn't exist. That "analyst" has a habit of making up or misinterpreting claims as "exclusive" info. If Cisco was actually a confirmed, public IFS customer, either they or Intel would have said so explicitly. He probably read Cisco's little soundbyte "support" for the creation of IFS and leapt to conclusions from there.

The custom part is an interesting statement if it's made internally. The word naturally leads into Intel IP but configured in a way desirable to the customer.

Yeah, but that would be completely in line with Intel's networking group. They already have many products like that shipping today. I missed the original statement when they talked about Intel 4 for networking, but if that still holds, this seems like the only realistic way it's going to happen.

Another note: Intel claims 2x density gains on the 4 process. Yes Meteorlake doesn't achieve that but maybe it's possible and we'll see that fully realized on certain products on the Intel 3 process.

Eh, maybe, but I doubt it. Even they have historically acknowledged the issues of measuring density by CPP x cell height. Congestion on lower level metal layers is a huge issue on modern nodes, and Intel 4/3 don't have PowerVia to help.

 

[jpiniero]

I could see nVidia going back to Samsung. But using an Intel Fab, yeah no.

 

[Exist50]

I could see nVidia going back to Samsung. But using an Intel Fab, yeah no.

Why not, if the price and process maturity were right? Nvidia has no real loyalties there.

 

[witeken]

Then I'm pretty sure it simply doesn't exist. That "analyst" has a habit of making up or misinterpreting claims as "exclusive" info. If Cisco was actually a confirmed, public IFS customer, either they or Intel would have said so explicitly. He probably read Cisco's little soundbyte "support" for the creation of IFS and leapt to conclusions from there.

https://twitter.com/x/status/1494355329106300928

You must include your own personal commentary when dropping links or quotes.

Daveybrat
AT Moderator

 

[jpiniero]

Why not, if the price and process maturity were right? Nvidia has no real loyalties there.

The process maturity won't be, that's the thing.

Maybe I could see packaging, if nVidia decides they want to use EMIB or Foveros for a future chiplet product. Maybe they could use Samsung for stuff they could get away with and save some money and TSMC for stuff that needs the power and density. But I wonder if TSMC's packaging would even work with non-TSMC chiplets.

 

[Exist50]

The process maturity won't be, that's the thing.

So you seriously believe Intel will not get 20A working, even with a slight delay? Come on, you're sounding like Charlie now.

 

[moinmoin]

Maybe I could see packaging, if nVidia decides they want to use EMIB or Foveros for a future chiplet product.

Good that you mention packaging. Considering essentially all existing advanced chiplets/tiles packaging approaches are currently foundry specific and Nvidia having a history of not wanting to be locked to a single foundry explains why Nvidia hasn't gone the chiplets route yet. I guess they will join once an open standard supported by all foundries appears. There is one, but it doesn't offer high enough bandwidth for usage in a GPU package.

 

[Doug S]

So you seriously believe Intel will not get 20A working, even with a slight delay? Come on, you're sounding like Charlie now.

What's your definition of "working"? When would you say Intel's 10nm was working? Was it in 2018 when they shipped 100K 10nm CPUs for the embedded market to meet a promise they had made to investors, or was it when they finally shipped real production quantities a couple years later?

Would you say Intel 7 is currently "working", or will they actually have to ship the server CPU (sorry don't keep up with their codenames) that has had 7 or 8 revisions and is still not working? I mean, you could argue that's not a problem with the process but with the design, but we simply don't know. Maybe the design sucks, or maybe yields of larger dies are awful and the repeated redesigns are to add redundancy so it yields well enough to show a profit. If Intel claims 20A is "working", but is hardly shipping anything on it does that count in your book?

It used to be easy in the past, Intel would give a quarter when they would begin shipments with a new process and it would happen in that quarter in massive quantities. With 14nm that went haywire, with 10nm it broke down completely. Until they show a track record of meeting commitments then I think belief that Intel will get a new process shipping before TSMC has an equivalent process shipping when today Intel has ZERO EUV chips in the wild versus TSMC which has over a billion, then yes I think quite serious people have good reason to be skeptical that Intel won't have 20A shipping on time, or with only a "slight" delay.

What I wonder is how ANYONE can seriously believe Intel's incredibly aggressive schedules, that they can leapfrog TSMC as well as introduce a new transistor type even though they have zero experience with mass production using EUV and have done nothing but break promises again and again for well over half a decade.

 

[Exist50]

Would you say Intel 7 is currently "working", or will they actually have to ship the server CPU (sorry don't keep up with their codenames) that has had 7 or 8 revisions and is still not working? I mean, you could argue that's not a problem with the process but with the design, but we simply don't know.

Yes, we do know. You can go out and buy all the Tiger Lake, Ice Lake, or Alder Lake you want. If it was a process issue that forced so many delays of Sapphire Rapids, then we certainly wouldn't be seeing the situation that we have with Alder Lake.

I'm not saying it's unreasonable to doubt Intel's claimed schedule, but let's not pretend that's anything more than a blind guess at this point.

 

[jpiniero]

I'm not saying it's unreasonable to doubt Intel's claimed schedule, but let's not pretend that's anything more than a blind guess at this point.

As I've been trying to say, Intel is going to sell pre-pre-pre risk production chiplets and whatever they get is whatever they get. An theoretical IFS customer isn't going to do that. Who knows how long it would take Intel to get any of I4/I3/20A/18A to a state where an IFS customer would seriously consider it. Probably never.

 

[RTX]

https://twitter.com/x/status/1574945058901692416

Horsecreek with the P550 cores with DDR5-5600
4mm x 4mm die