Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[Thala]

I know sometime they can peak 7w or 9w but average power consumption is way below that most of time 3w to 4W.

And in mobile there is soc not just cpu and Gpu, it need to power modem, bluetooth, wifi and other things, so that 5W envelope include things like that.

3W-4W is total system power (not just only the SoC) including the modem, screen etc. under sustainable conditions. For example the Samsung Galaxy S21 Ultra is drawing less than 3W system power - with screen brightness set to minimum.
Andrei did publish some peak and sustained values for different phones last year here

 

[Ajay]

If I'm correct at what you're referring to, ain't that just the contact which energizes the gate?

The gate is wrapped around the channel between source and drain if that is what you are referring to. The gold colored area.

If you mean the blue pillar thing, that looks like the gate contact attaching to the poly.

I think you are both right. Thinking about it last night, I was wondering how a single channel device can drive enough current for HP logic. So, maybe this is for LP devices?
The second graphic says 'beyond nanosheet' - so IBM must be projecting forward something like 5 years or more. Clearly, well, to me, an R&D project at this point.

Seems to me that stacking nanosheets will be the better solution for sometime to come. High NA EUV will allow a reduction in dimensions like 'active width' with more (vertical) nanosheet stacks.

 

[eek2121]

I know sometime they can peak 7w or 9w but average power consumption is way below that most of time 3w to 4W.

And in mobile there is soc not just cpu and Gpu, it need to power modem, bluetooth, wifi and other things, so that 5W envelope include things like that.

I am aware. However, typical power consumption for even laptop chips is pretty low. We are talking about peak GPU performance. My point is that RDNA2 cores @ 1.9 GHz are completely doable assuming a competent process is used. Samsung, of course, wanted to use their own process, which has a long history of heat and power issues. That is a big reason why NVIDIA's current gen cards have such a high TDP and use so much power.

 

[Doug S]

Qualcomm would be a great customer win. Intel can't afford to discount much, IMHO. Plus, as soon as Intel offered the 'real' price on the next chip, QCOM would jump to Samsung. The hard part is the time it would take for Intel to ramp up their foundry. Look how long it took TSMC - and the switch by Apple from Samsung was the catalyst that really got TSMC onto a good cutting edge cadence. IIRC, Apple started out by buying up all TSMC's risk wafer production. Deal of the century to jump start TSMC.

Do you have a reference for that? I'm not sure how that would even work, since Apple went sole source with TSMC for A8 on 20nm then dual sourced A9 on 16FF TSMC / 14nm Samsung. I always thought that was weird, as would think that the way Apple would switch suppliers would want to dual source for a year or two, not fully switch then switch back to dual source then fully switch again - unless A8 was dual sourced but Apple's deal with Samsung allowed them to take zero wafers and when TSMC was able to provide enough volume so too bad for Samsung.

 

[jpiniero]

Do you have a reference for that? I'm not sure how that would even work, since Apple went sole source with TSMC for A8 on 20nm then dual sourced A9 on 16FF TSMC / 14nm Samsung. I always thought that was weird, as would think that the way Apple would switch suppliers would want to dual source for a year or two, not fully switch then switch back to dual source then fully switch again - unless A8 was dual sourced but Apple's deal with Samsung allowed them to take zero wafers and when TSMC was able to provide enough volume so too bad for Samsung.

The A9 dual source was more about GloFo but that part ended up not happening.

 

[Thala]

I am aware. However, typical power consumption for even laptop chips is pretty low.

We are not talking typical power consumption but thermal dissipation capacity under full load, which for phones is 3-4W at system level (including the screen).

 

[Exist50]

We are not talking typical power consumption but thermal dissipation capacity under full load, which for phones is 3-4W at system level (including the screen).

Phones can definitely dissipate more than 3-4W total under full load. 5W is a good estimate for the SoC alone.

 

[Thala]

Phones can definitely dissipate more than 3-4W total under full load. 5W is a good estimate for the SoC alone.

This is not the case - 5W would be close to impossible to sustain. You can refer to Andrei's system power measurements, where for instance the Galaxy S21 goes down to a sustainable 2.8-2.9 W (Snapdragon 888) and 3.7-4W (Exynos) system power - not even close to 5W - let alone when looking at only the SoC.
What makes you think that the upcoming Samsung Galaxy could achieve a revolutionary thermal dissípation capabilities such that the SoC could sustain 5W?

 

[Ajay]

Do you have a reference for that? I'm not sure how that would even work, since Apple went sole source with TSMC for A8 on 20nm then dual sourced A9 on 16FF TSMC / 14nm Samsung. I always thought that was weird, as would think that the way Apple would switch suppliers would want to dual source for a year or two, not fully switch then switch back to dual source then fully switch again - unless A8 was dual sourced but Apple's deal with Samsung allowed them to take zero wafers and when TSMC was able to provide enough volume so too bad for Samsung.

Sorry, don't know when Apple started buying out risk wafers. Pretty sure I read it on these forums, or from a link posted in CPU&O.

 

[Roland00Address]

Do you have a reference for that? I'm not sure how that would even work, since Apple went sole source with TSMC for A8 on 20nm then dual sourced A9 on 16FF TSMC / 14nm Samsung. I always thought that was weird, as would think that the way Apple would switch suppliers would want to dual source for a year or two, not fully switch then switch back to dual source then fully switch again - unless A8 was dual sourced but Apple's deal with Samsung allowed them to take zero wafers and when TSMC was able to provide enough volume so too bad for Samsung.

Apple switched once again exclusively to TSMC not just due to the superior process but because of the packaging technology allowing to put the ram directly on top of the soc allowing a thinner device and half a dozen other benefits.

 

[moinmoin]

Excellent (and funny) technical video on the challenges of EUV and High-NA:

My guess is Intel wants to focus on High-NA for its higher throughput while avoiding EUV multi-pattering, though I'm not sure whether they manage to bring it on on time (after all they didn't for plain EUV). And plain EUV with multi-pattering on more deprecated machines may be more economical for some time.

 

[Doug S]

And plain EUV with multi-pattering on more deprecated machines may be more economical for some time.

"Plain EUV" (I assume you mean non high NA?) scanners will not be deprecated for a very long time. Smaller nodes will eventually use high NA EUV to avoid multiple patterning with EUV, but it will be for only a few critical layers. The current non high NA EUV scanners will be used for the rest of the layers.

The reason EUV replaced DUV so quickly in just a couple nodes (N3 uses EUV in most layers with not a whole lot of DUV layers) is because they'd been layering on more and more multipatterning steps with each generation for years. IIRC Intel began using it at 45nm and TSMC at 28nm. First for line cutting, and the next nodes weren't even possible without multipatterning and soon after that requiring full computational lithography to enhance beyond what multipatterning alone could do. There was no choice since there was nothing better on the horizon until EUV was finally made to work.

Today there is something better on the horizon, so they won't need to push "plain EUV" forward for a half dozen nodes with SADP and even some SAQP steps throughout the stack as was the case with DUV, so there won't be a fast switch to high NA EUV for a bunch of layers in short order like there was when the EUV transition finally occurred.

 

[oak8292]

I think EUV was so late that double patterning hasn't really gone away. Here is quote from a Scotten Jones article;

"TSMC’s 5nm process currently in production has a 28nm M0 pitch and we believe this one layer may be double patterned EUV in current production while the rest of the layers that use EUV are single patterned. For TSMC’s 3nm process due to begin risk starts later this year we expect several EUV double patterned metal layers. With the current timing for 0.55NA systems to enter production estimated to be in the 2025/2026 time-frame, we may see foundry 2nm and Intel 5nm processes in production before then with extensive EUV double pattering."

SPIE 2021 – ASML DUV and EUV Updates - Semiwiki

At the SPIE Advanced Lithography Conference held in February, ASML presented the latest information on their Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) exposure systems. I recently got to interview Mike Lercel of ASML to discuss the presentations. DUV Despite all the attention EUV is...

semiwiki.com

The economics are starting to get fairly extreme with 0.55 NA EUV running up in the $300 million per machine range. TSMC is still talking gigafab at N3 but N2 and lower the amount of silicon produced may be limited to tiles. IO is starting to get disaggregated (EPYC and AWS Graviton 3) and AMD is enhancing their SRAM with separate die. Everything from N2 may be 'tiles' or 'chiplets'.

 

[moinmoin]

"Plain EUV" (I assume you mean non high NA?) scanners will not be deprecated for a very long time.

I was referring to "deprecation" in a financial sense of course. I sure hope it won't take "a very long time" for TSMC to have paid off the cost of the EUV machines and be able to use them for lower throughput processes that currently make no financial sense like e.g. quad pattering and beyond.

 

[Doug S]

I was referring to "deprecation" in a financial sense of course. I sure hope it won't take "a very long time" for TSMC to have paid off the cost of the EUV machines and be able to use them for lower throughput processes that currently make no financial sense like e.g. quad pattering and beyond.

You mean depreciation then, not deprecation.

 

[moinmoin]

You mean depreciation then, not deprecation.

Thanks for the correction, as a non-native speaker I indeed overlooked that one i difference.

 

[Markfw]

Thanks for the correction, as a non-native speaker I indeed overlooked that one i difference.

Slightly OT, but I just had to say, I appreciate people that admit this. English is not everyone's native language, and its not easy to master.

 

[Mopetar]

Slightly OT, but I just had to say, I appreciate people that admit this. English is not everyone's native language, and its not easy to master.

Even native English speakers screw stuff like that up all the time as well. English is pretty much the bastard tongue of the world and has a linguistic pedigree that resembles your average mutt in the city kennel.

 

[Doug S]

Even native English speakers screw stuff like that up all the time as well. English is pretty much the bastard tongue of the world and has a linguistic pedigree that resembles your average mutt in the city kennel.

Native English speakers confuse their, there and they're and stuff like that all the time, so I don't really have a problem with someone who confuses depreciation and deprecation as a non-native speaker!

While I took four years of German in high school I've mostly forgot and picked up just enough to almost get by when traveling in Spanish, French and Arabic, I've probably been asking people where I can get a cow to the airport or asking for a hotel ceiling for the night and they figure out what I meant.

 

[soresu]

Native English speakers confuse their, there and they're and stuff like that all the time, so I don't really have a problem with someone who confuses depreciation and deprecation as a non-native speaker!

Eh, it's more of a problem when writing on a phone with autocorrect enabled 😱

 

[geegee83]

Native English speakers confuse their, there and they're and stuff like that all the time, so I don't really have a problem with someone who confuses depreciation and deprecation as a non-native speaker!

While I took four years of German in high school I've mostly forgot and picked up just enough to almost get by when traveling in Spanish, French and Arabic, I've probably been asking people where I can get a cow to the airport or asking for a hotel ceiling for the night and they figure out what I meant.

The most common mistake in tech forums seem to be “loosing”

Correct: B is losing to C. B loses.
Wrong: B is loosing to C. B looses.

 

[Thunder 57]

The most common mistake in tech forums seem to be “loosing”

Correct: B is losing to C. B loses.
Wrong: B is loosing to C. B looses.

That is a pet peeve of mine. It's like people saw "loosing" and figured that was correct.

 

[Saylick]

Uh oh. China realizes that it's 2025 plan to develop their own semiconductor industry is not progressing as fast as they'd like, so they are rolling out a plan to "collaborate" with foreign semiconductor companies to help develop IP, which may include the transfer of prior IP. This sounds like yet another one of China's ploys where a domestic entity and a foreign entity are required to work together if the foreign entity wants to do business in China, only for the Chinese entity to learn all they can before they dump the foreign entity to the curb.

According to the article, they're targeting Intel, AMD, ASML, and Infineon, amongst other companies. You know, the big players.

China to launch chipmaking platform as it targets Intel and AMD

U.S. likely to object to Beijing's efforts for independent supply chain

asia.nikkei.com

 

[Thunder 57]

Uh oh. China realizes that it's 2025 plan to develop their own semiconductor industry is not progressing as fast as they'd like, so they are rolling out a plan to "collaborate" with foreign semiconductor companies to help develop IP, which may include the transfer of prior IP. This sounds like yet another one of China's ploys where a domestic entity and a foreign entity are required to work together if the foreign entity wants to do business in China, only for the Chinese entity to learn all they can before they dump the foreign entity to the curb.

According to the article, they're targeting Intel, AMD, ASML, and Infineon, amongst other companies. You know, the big players.

China to launch chipmaking platform as it targets Intel and AMD

U.S. likely to object to Beijing's efforts for independent supply chain

asia.nikkei.com

The sad thing is there's a good chance they will fall for it. Everybody wants that damn Chinese market. Just look at how the NBA sucks uo ti them.

 

[Doug S]

Uh oh. China realizes that it's 2025 plan to develop their own semiconductor industry is not progressing as fast as they'd like, so they are rolling out a plan to "collaborate" with foreign semiconductor companies to help develop IP, which may include the transfer of prior IP. This sounds like yet another one of China's ploys where a domestic entity and a foreign entity are required to work together if the foreign entity wants to do business in China, only for the Chinese entity to learn all they can before they dump the foreign entity to the curb.

According to the article, they're targeting Intel, AMD, ASML, and Infineon, amongst other companies. You know, the big players.

China to launch chipmaking platform as it targets Intel and AMD

U.S. likely to object to Beijing's efforts for independent supply chain

asia.nikkei.com

They don't really have any leverage to force any of the above companies to cooperate with this. Sticks won't work, so they'll need one hell of a big carrot. And they know going in China's goal is to steal their IP, so why would they believe any lofty talk about "collaboration"?