Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[eek2121]

But mobile soc rarely reach those figures, usually they consume between 3W to 5W when you play heavy game like Genshini Impact.

Probably Samsung overpromise with 2Ghz figures but still its impressive if they can Cool 1.2ghz Gpu in smartphone.

Today's mobile SoCs use closer to 7W or even 9W at peak. I promise you, RDNA2 is not the issue. If Van Gogh, the CPU in the Steam Deck, received a shrink to TSMC N5, clocks would go up and power consumption would drop considerably. Van Gogh would likely consume 7-9W at peak with clocks close to the target, and it has more CUs.

EDIT: I also think a lot of people don't realize how efficient AMD's chips are, especially at TSMC. Ask yourself what would happen if a chip like the 6800U (15W-28W), with 8 CPU cores @ 2.7-4.7 GHz and 12 CUs @ 2.2 GHz were shrunk to TSMC N5 and received a slight reduction in specs (Maybe 6 CUs instead of 12, a drop in CPU clocks or a slight reduction in cores, though if AMD's marketing slides are to be believed, you may not need to touch the GPU or CPU). It would probably consume close to what a phone SoC would consume, and it'd be far more powerful than current Android SoCs. Of course, AMD doesn't have the capacity to even think about that...

 

[Khato]

Today's mobile SoCs use closer to 7W or even 9W at peak. I promise you, RDNA2 is not the issue. If Van Gogh, the CPU in the Steam Deck, received a shrink to TSMC N5, clocks would go up and power consumption would drop considerably. Van Gogh would likely consume 7-9W at peak with clocks close to the target, and it has more CUs.

EDIT: I also think a lot of people don't realize how efficient AMD's chips are, especially at TSMC. Ask yourself what would happen if a chip like the 6800U (15W-28W), with 8 CPU cores @ 2.7-4.7 GHz and 12 CUs @ 2.2 GHz were shrunk to TSMC N5 and received a slight reduction in specs (Maybe 6 CUs instead of 12, a drop in CPU clocks or a slight reduction in cores, though if AMD's marketing slides are to be believed, you may not need to touch the GPU or CPU). It would probably consume close to what a phone SoC would consume, and it'd be far more powerful than current Android SoCs. Of course, AMD doesn't have the capacity to even think about that...

Let's start with the Steam Deck. I believe that is spec'd at 4-15W with an 8CU GPU in the 1-1.6GHz range. At maximum frequency that's 1.6TFLOPS, but that's almost certainly going to be closer to the 15W end of the power budget. Reducing the power by 40% to account for n7 -> n5 brings that down to 9W. So from that example we might see 1.6 TFLOPS in something approaching a smartphone SoC power budget... which is pretty much exactly where the Adreno 660 in the Snapdragon 888 sits.

Now with respect to the 6800U, 12CU at 2.2GHz and 28W is pretty much exactly where you'd expect compared to the Steam Deck given the slight process improvement. (Slightly over twice the TFLOPs at a bit under twice the power - process gains are negated by frequency increase.) The same exercise can be repeated with the discrete cards, just need to account for the additional power draws outside of the GPU. It all matches up quite well.

So that brings us to the Exynos 2200 implementation - 6CU at the target 1.9GHz would yield 1.46TFLOP. Note how that's below last year's Snapdragon. 1.3GHz is only 1TFLOP. And while TFLOPs aren't directly comparable across architectures, they are indicative of performance levels. But unlike the desktop realm where RDNA2 performs better than Ampere per TFLOP the situation will likely be reversed in the mobile space where the architectures have been optimized for those workloads.

 

[Doug S]

So like many of us kept saying, TSMC is not taking N3 capacity from other customers for Intel. Hopefully this puts an end to the claims it is some evil Intel plan to hamstring AMD.

 

[Ajay]

台積電寶山研發中心急轉彎　英特爾、蘋果訂單王不見王

台積電原本竹科寶山將建置的研發中心先前已迅速改為3奈米生產據點，更重要是只服務英特爾(Intel)，此舉將使英特爾重要機密產品與另一大客戶蘋果(Apple)分開。

www.digitimes.com.tw

In addition, Samsung's 3nm GAA is still in the training period and does not pose any threat to TSMC until 2025.

. NOT GOOD. Man, Samsung is Korea's Intel

 

[Hitman928]

So like many of us kept saying, TSMC is not taking N3 capacity from other customers for Intel. Hopefully this puts an end to the claims it is some evil Intel plan to hamstring AMD.

Yep. Intel is basically fronting a ton of money to allow TSMC to build out supply of its most advanced node. Gives one pause about putting faith into Intel's fab roadmap, if you didn't already have doubts.

 

[Ajay]

Yep. Intel is basically fronting a ton of money to allow TSMC to build out supply of its most advanced node. Gives one pause about putting faith into Intel's fab roadmap, if you didn't already have doubts.

While I expect Intel to produce GPUs at TSMC for a while, one does really have to wonder if this is a 'one off' deal for compute chiplets or something else. Intel is supposedly hedging their bets till 20A and High NA EUV. We will see. Not enough spies in Intel to tell us what's going on (well, not ones that talk in anyway to the public).

 

[Doug S]

Yep. Intel is basically fronting a ton of money to allow TSMC to build out supply of its most advanced node. Gives one pause about putting faith into Intel's fab roadmap, if you didn't already have doubts.

Even if Intel was 90% confident of their roadmap, they might want to have a backup plan. They were able to escape mostly unscathed (at least based on their revenue/profit figures) from their 10nm disaster because AMD has only hit their stride in the last couple years. They can't afford another one, and having 40K wpm of N3 at the very least guarantees them equivalent or better process technology than AMD through 2025 no matter what happens in Intel fabs. If Intel fabs can produce better than N3 stuff then the N3 stuff serves the mainstream market instead of the high end.

 

[jpiniero]

Even if Intel was 90% confident of their roadmap, they might want to have a backup plan. They were able to escape mostly unscathed (at least based on their revenue/profit figures) from their 10nm disaster because AMD has only hit their stride in the last couple years. They can't afford another one, and having 40K wpm of N3 at the very least guarantees them equivalent or better process technology than AMD through 2025 no matter what happens in Intel fabs. If Intel fabs can produce better than N3 stuff then the N3 stuff serves the mainstream market instead of the high end.

2-3 billion a quarter is a ton of money. Even for Intel.

 

[Ajay]

2-3 billion a quarter is a ton of money. Even for Intel.

Yeah, pissing on Steve Jobs will live on forever in infamy at Intel. They need some big ARM SoC companies to move over to IDM 2.0. Maybe if they get their stuff together at 40 or 20A, they'll have a chance. Or not. Nvidia would be a AAA customer win, but, Hahahahahahahahahahahaha.....

 

[DisEnchantment]

. NOT GOOD. Man, Samsung is Korea's Intel

Taiwan Media always negative about Samsung for obvious reasons, but fine.

I guess both Intel and Samsung are not trying to fight TSMC anymore on FinFET.
Just rushing to RibbonFET and MBCFET. N3 is not so big a deal anyway once they get close enough to N4 (Intel 4 & 4LPP )

I am still hopeful Intel and Samsung will get their act together. IBM and Samsung are collabing on GAAFET and VTFET.
Fingers crossed on Samsung 3GAE this year. They got the Cadence and Synopsys tools already up since a while.
From SAFE Forum, Oct 2021.

Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023.

Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices

Details were disclosed at the company’s 5th Annual Samsung Foundry Forum

news.samsung.com

 

[DrMrLordX]

Intel is supposedly hedging their bets till 20A and High NA EUV. We will see. Not enough spies in Intel to tell us what's going on (well, not ones that talk in anyway to the public).

See below.

2-3 billion a quarter is a ton of money. Even for Intel.

That's money Gelsinger can't pour into fab research and development. It will come back to bite them.

Fingers crossed on Samsung 3GAE this year. They got the Cadence and Synopsys tools already up since a while.

I heard from at least one poster here that 3GAE may never see the market, and that we'll have to wait for 3GAP in Q3 (or later)?

 

[DisEnchantment]

I heard from at least one poster here that 3GAE may never see the market, and that we'll have to wait for 3GAP in Q3?

That was the sentiment until late of last year with articles like this

Samsung Foundry 3nm Gate All Around Process Node, 3GAE, Delayed To As Late As 2024

Samsung Foundry 3nm Gate All Around Process Node, 3GAE, Delayed to 2024! This would arrive in a similar time frame to TSMC’s denser 2nm GAA technology. Samsung and Intel continue to slip furt…

semianalysis.com

Even Andrei and Ian were tweeting about delays

I also wrote this from mid of last year.

Samsung 3GAE gutted and delayed, 3GAE could be behind 4LPE it looks like.
2019

2021
View attachment 46533

New 4LPP/5LPP/8LPA node has been introduced
From IEDM 2020,
On an A75 Core : 7LPP -> 4LPE : 23% speed improvement (actual), 7LPP -> 4LPP : 29% speed improvement (estimated)
On an A57 Core : 7LPP -> 4LPE : 33% efficiency improvement (actual), 7LPP -> 4LPP : 46% efficiency improvement (estimated)
Details behind paywall.

Samsung Details 5nm and 4nm; Adds 8LPA, 5LPP, and 4LPP Nodes; Readies 3nm GAA For Next Year

Samsung revealed more details of its 5LPE process technology which recently ramped, gave a roadmap status update along with new stop-gap nodes announcement.

fuse.wikichip.org

TSMC official figures, on paper
N7 -> N3 : 32% speed improvement
N7 -> N3 : 69% efficiency improvement

In 2H2022, 4LPP will be ~4% less perf than N3 and a very significant ~15% less efficient. Theoretical logic density probably 30 - 35% behind N3.
Density not so big a deal, HPC devices cannot extract as much density as advertised by TSMC. Certain NV devices using 8N have higher density than AMD's N7P devices.
Another setback for Samsung.

For NV in 2H2022, if they are moving from 8N -> 5LPP, the jump is insane. And nobody to compete with for wafers.
8LPU -> 5LPP : 27% speed improvement (estimated)
8LPU -> 5LPP : 45% efficiency improvement (estimated)

8LPA probably for automotive chips.

Then Samsung came out in the virtual event from 2 months ago, SFF 2021/Oct-Nov and said 3GAE is launching in H1 2022, with not so gutted values as reported by Dylan.

Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices

Details were disclosed at the company’s 5th Annual Samsung Foundry Forum

news.samsung.com

We will see, while not really optimistic, still hopeful Samsung will have its day in the sun.

 

[The Hardcard]

Is there time for a new die? Assuming they were verifying and testing the die since 2 weeks before they released the January 11 date. Sometime in the last week of December they identify some major issues.

Can they have the revision available by February 8 to show, then say product availability will be early April?

It’s not out of the question that it could be just a power management issue.

 

[DrMrLordX]

We will see, while not really optimistic, still hopeful Samsung will have its day in the sun.

Samsung has a lot to prove, such as Exynos 2200 being ready by Feb 8th (or so).

 

[Doug S]

Samsung has a lot to prove, such as Exynos 2200 being ready by Feb 8th (or so).

Just because they plan to announce the new Galaxy phones on Feb 8th doesn't mean they need to start shipping them then. Haven't they delayed shipment until May at least once before?

Doing demos doesn't require Exynos 2200 to run its GPU at full speed, though it would limit their ability to crow about GPU performance gains. They could claim they don't want to tip their hand to the competition and "you'll have to wait until they ship to see how fast they are".

 

[Doug S]

Yeah, pissing on Steve Jobs will live on forever in infamy at Intel. They need some big ARM SoC companies to move over to IDM 2.0. Maybe if they get their stuff together at 40 or 20A, they'll have a chance. Or not. Nvidia would be a AAA customer win, but, Hahahahahahahahahahahaha.....

Qualcomm is the most likely candidate, since they have switched between TSMC and Samsung already for better pricing/availability. Intel certainly has form in paying people to take products they wouldn't otherwise want in the mobile market...

Taiwanese firms like Mediatek or Rockchip aren't going to, Apple's appetite for leading edge wafers is too large for Intel to consider unless/until their foundry business gets bigger than their in-house business. The remaining ARM SoC OEMs are too small to matter.

 

[Ajay]

Taiwan Media always negative about Samsung for obvious reasons, but fine.

True - I have a habit of forgetting that.

I am still hopeful Intel and Samsung will get their act together. IBM and Samsung are collabing on GAAFET and VTFET.

Yes, this look easy to manufacture (left) . The right looks better, but I can't tell from such a simple graphic, wth the advantage is.

For NV in 2H2022, if they are moving from 8N -> 5LPP, the jump is insane. And nobody to compete with for wafers.

I just wonder if NV wasn't confident about the timeline for 5LPP - seems like it would have been a great fit (except for Hopper).

 

[Ajay]

Qualcomm is the most likely candidate, since they have switched between TSMC and Samsung already for better pricing/availability. Intel certainly has form in paying people to take products they wouldn't otherwise want in the mobile market...

Taiwanese firms like Mediatek or Rockchip aren't going to, Apple's appetite for leading edge wafers is too large for Intel to consider unless/until their foundry business gets bigger than their in-house business. The remaining ARM SoC OEMs are too small to matter.

Qualcomm would be a great customer win. Intel can't afford to discount much, IMHO. Plus, as soon as Intel offered the 'real' price on the next chip, QCOM would jump to Samsung. The hard part is the time it would take for Intel to ramp up their foundry. Look how long it took TSMC - and the switch by Apple from Samsung was the catalyst that really got TSMC onto a good cutting edge cadence. IIRC, Apple started out by buying up all TSMC's risk wafer production. Deal of the century to jump start TSMC.

 

[Hitman928]

True - I have a habit of forgetting that.


View attachment 55928

Yes, this look easy to manufacture (left) . The right looks better, but I can't tell from such a simple graphic, wth the advantage is.



I just wonder if NV wasn't confident about the timeline for 5LPP - seems like it would have been a great fit (except for Hopper).

I haven't looked into VTFETs much, but the main benefit that I am aware of is density. Basically, by constructing the channel in the vertical direction you are able to squeeze in a lot more FETs into the same area. I would imagine it should reduce parasitics as well. Something else to read up on during the weekends, lol.

 

[Saylick]

View attachment 55928

Yes, this look easy to manufacture (left) . The right looks better, but I can't tell from such a simple graphic, wth the advantage is.

If the gold thing is the channel, I'm not sure what the one on the right is doing but it sure as heck looks like a regular ol' FinFET to me. Is this diagram just comparing VTFETs with FinFETs? Or are both of these VTFETs?

 

[Ajay]

Right is some sort of upside down FinFET??? With two metal gate contacts dropping down. Left is a VTFET. There should be more colors, because elements of the VTFET are too hard to determine. They seem to have stripped out SI and SIO2. What is the polished brass stuff - contacts again, why so many segments. They could be transitional stages in the build up of the xtor. I shouldn't have posted these since I can't find anymore detail on the web. Here's the only other illustration I could find:



A little better, but what is that weird vertical 'knob' bit?

 

[Saylick]

A little better, but what is that weird vertical 'knob' bit?

If I'm correct at what you're referring to, ain't that just the contact which energizes the gate?

 

[Hitman928]

Right is some sort of upside down FinFET??? With two metal gate contacts dropping down. Left is a VTFET. There should be more colors, because elements of the VTFET are too hard to determine. They seem to have stripped out SI and SIO2. What is the polished brass stuff - contacts again, why so many segments. They could be transitional stages in the build up of the xtor. I shouldn't have posted these since I can't find anymore detail on the web. Here's the only other illustration I could find:

View attachment 55946

A little better, but what is that weird vertical 'knob' bit?

The gate is wrapped around the channel between source and drain if that is what you are referring to. The gold colored area.

If you mean the blue pillar thing, that looks like the gate contact attaching to the poly.

 

[hemedans]

Today's mobile SoCs use closer to 7W or even 9W at peak. I promise you, RDNA2 is not the issue. If Van Gogh, the CPU in the Steam Deck, received a shrink to TSMC N5, clocks would go up and power consumption would drop considerably. Van Gogh would likely consume 7-9W at peak with clocks close to the target, and it has more CUs.

EDIT: I also think a lot of people don't realize how efficient AMD's chips are, especially at TSMC. Ask yourself what would happen if a chip like the 6800U (15W-28W), with 8 CPU cores @ 2.7-4.7 GHz and 12 CUs @ 2.2 GHz were shrunk to TSMC N5 and received a slight reduction in specs (Maybe 6 CUs instead of 12, a drop in CPU clocks or a slight reduction in cores, though if AMD's marketing slides are to be believed, you may not need to touch the GPU or CPU). It would probably consume close to what a phone SoC would consume, and it'd be far more powerful than current Android SoCs. Of course, AMD doesn't have the capacity to even think about that...

I know sometime they can peak 7w or 9w but average power consumption is way below that most of time 3w to 4W.

And in mobile there is soc not just cpu and Gpu, it need to power modem, bluetooth, wifi and other things, so that 5W envelope include things like that.

 

[DrMrLordX]

Just because they plan to announce the new Galaxy phones on Feb 8th doesn't mean they need to start shipping them then. Haven't they delayed shipment until May at least once before?

Doing demos doesn't require Exynos 2200 to run its GPU at full speed, though it would limit their ability to crow about GPU performance gains. They could claim they don't want to tip their hand to the competition and "you'll have to wait until they ship to see how fast they are".

Exynos 2200 demo was supposed to be at CES. Samsung was a no-show, and instead said that they would showcase the chip AND the phone in February. If they choose not to show the full capabilites of the phone then there will be quite a stink over it, especially considering that Gen 1 phones should be shipping already. In fact the Xiaomi 12 series phones are shipping in mainland China right now.