Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[SiliconFly]

Pfft Intel had 6 GHz+ chips years ago. Unless for some reason you're discounting overclockers, which renders the distinction moot if you do.



Careful, I've suggested that before but the e-core fans won't have any of it.

Actually, I love the E-cores!

 

[A///]

I think we're actually discussing about the size of a single p-core. It is larger than it needs to be (for example, compared to the size of a single Zen 4 core).

Given Intel's situation and finances, I think they may have realised doing so would cut into their production time and thus cost them dearly. It's easier to push an "inferior" p core size than spend the capital on shrinking it. Or getting ht to run on the e cores due to the mismatch circumstances.

 

[JoeRambo]

I think we're actually discussing about the size of a single p-core. It is larger than it needs to be (for example, compared to the size of a single Zen 4 core).

Where is the comparison of Zen4 vs P-core on ISO process? How can we even compare something that has different amount of L2 per core, heck even L3 cache slice requirements are completely different.
The best comparison comes from MTL compute die 6P+8E, giving 8 units of compute total and comparing that to AMD's CCD for Zen4.

 

[SiliconFly]

Given Intel's situation and finances, I think they may have realised doing so would cut into their production time and thus cost them dearly. It's easier to push an "inferior" p core size than spend the capital on shrinking it. Or getting ht to run on the e cores due to the mismatch circumstances.

Usually, developing a new performance core is very difficult, expensive & time consuming. But what many overlook is the fact that it's extremely risky too. It's a massive commitment & if it fails, the repercussions are severe. Like bulldozer.

Lion Cove hopefrully is a step in the right direction. But it's hard to say whether it'll succeed in the real world until actually it does.

 

[A///]

Usually, developing a new performance core is very difficult, expensive & time consuming. But what many overlook is the fact that it's extremely risky too. It's a massive commitment & if it fails, the repercussions are severe. Like bulldozer.

Lion Cove hopefrully is a step in the right direction. But it's hard to say whether it'll succeed in the real world until actually it does.

Never thought I'd see the day to see a chatgpt style reply reiterating what I said.

 

[SiliconFly]

Where is the comparison of Zen4 vs P-core on ISO process? How can we even compare something that has different amount of L2 per core, heck even L3 cache slice requirements are completely different.
The best comparison comes from MTL compute die 6P+8E, giving 8 units of compute total and comparing that to AMD's CCD for Zen4.

Actually I was just saying what I read a while back. Something like a single Zen core was only half the size of a single Intel p-core (excluding L2). Just googled & found this on reddit posted by @Geddagod. Check it out... (link)

It says: "The whole Golden Cove module is 86 percent larger than the Zen 3 module, while the core itself is 74 percent larger".

I love Intel a lot, but I just cannot lie in this case. Current Intel P-core are c*** that shouldn't even exist in this day and age. The P-cores are extremely fat & power-hungry. I seriously wish that the new LNC core is more comparable to a Zen core rather than the existing Intel P-core.

 

[JoeRambo]

I love Intel a lot, but I just cannot lie in this case. Current Intel P-core are c*** that shouldn't even exist in this day and age. The P-cores are extremely fat & power-hungry. I seriously wish that the new LNC core is more comparable to a Zen core rather than the existing Intel P-core.

That is unfortunately load of uninformed BS and goal post switching ( we were talking about GLC vs ZEN4, and suddenly ZEN3 comparison is thrown in ).
Are you aware that GLC includes AVX512 and full wide execution units? Just so You know, having PRF for 512bit registers does not come free in area and neither do full width vector ALU/FMA units, neither is massive L1D bw.

So while Intel's retarded ways of AVX512 etc disable were discussed here ad infinitum, one cannot compare Z3 and GLC and claim that it's not area efficient. Some Intel defence force dude might claim that GLC is very area efficient when executing some AVX512 code and he'd be right ( even if argument is not really valid on desktop ).

The real comparison would be Z4 and GLC on same process, both without L2. But even this comparison is disingenuous from "performance" side, as now AMD is supporting AVX512 and benefiting from performance increases and Intel is continuing to carry massive area that is not used.

IF Intel were to produce a proper client P-core without AVX512 waste, it would not be THAT much larger than Zen4 on SAME process (except Z4 would continue to support and benfit from avx512 obviuosly). AMD funnily is spending almost no area on AVX512, their PRF is still 256bits and execution units also. Kudos and all credit for them for finding such clever tricks.

 

[SiliconFly]

without AVX512 waste... it would not be THAT much larger than Zen4 on SAME process. AMD funnily is spending almost no area on AVX512,

You maybe right. But you also agree that it's still carrying the avx512 dead weight.

Next is, you also say AMD spends almost no area on AVX512 while also saying Intel p-core dead space is mainly due to AVX512 support. What the reason for the discrepancy?

Also, Intel P-Cores are know for their high power-inefficiency. It's a well established fact. Don't get me wrong. I actually like Intel a lot. But I strongly believe LNC is the way to go. Time to retire the fat/inefficient cores.

 

[qmech]

Again no. Where did I claim it's the greatest thing since sliced bread? I'd appreciate it if you didn't make up wild and ludicrous claims of things I've never stated on here. SMIC 7nm is still 5 years minimum behind cutting edge and it will have a limit of what's possible going forward. Unless SMIC or China can get their hands on EUV machines which need maintenance to maintain production or have access to the chemicals needed, or heck, make their own, they're still screwed by sanctions.

Please show me where I'm even remotely excited about SMIC doing this. If it isn't clear by now I personally prefer other countries relying on the west to survive, not doing their own thing.

Sure: https://forums.anandtech.com/thread...g-foundry-intel.2579857/page-64#post-41070756

"knocked it out of the park" was the exact phrase you used.

I responded by simply pointing out that the TechInsight summary did not make any claims that backed up the "knocked it out of the park" conclusion, to which you started off on the Intel7 tangent, clearly preferring that to the subject matter. I apologize for continuing on the Intel7 issue, derailing this thread for several pages. That was clearly not worth it and I will not continue arguing those particular semantics other than to state that I disagree with your evaluation of Intel7 compared to N7.

 

[JoeRambo]

Time to retire the fat/inefficient cores.

Again, that is load of nonsense. Why not go along Your pseudo logic a bit further and shout "Zen4 is area INEFFICIENT, lets retire it in favour of Zen4C, a new pinnacle of efficiency on TSMC 5nm".
Oh wait, so now your core has actual requirement to clock 6ghz? What about other possible requirements like including full width AVX512? 1024bytes per clock from L1D? are they invalid cause You believe so?

 

[qmech]

SMIC N+2 in Huawei Mate Pro 60 - Semiwiki

Up until last December I was president and owner of IC Knowledge LLC, at the end of November, I sold IC Knowledge LLC to TechInsights. It has been interesting to become an insider at the world’s leading semiconductor reverse engineering and knowledge company. The latest SMIC N+2 analysis is an...

semiwiki.com

SMIC Mass Produces 14nm Nodes, Advances To 5nm, 7nm

SMIC ramps up 14nm production, proceeds with sub-10nm technologies.

www.tomshardware.com

So they jumped from 14nm to 7nm in about one year? Isn't that impressive?

I'm not entirely sure where you get the "one year" from. SMIC had at least one N+1 7nm chip last year, so in one year they've optimized their 7nm process (a fair bit, maybe).

It's worth noting that SMIC aren't the ones touting their process. For obvious reasons, they are being extremely cautious about flaunting their most advanced nodes. You will not find any press releases from them claiming a 7 nm process node. You will not even find mention of anything below 28 nm on their website. Even in their regulatory filings, investor reports, and quarterly reports, 14 nm and below is lumped together as "FinFET nodes". There are no details (or mentions) of 14 nm, 10 nm, 7 nm, etc.

I doubt any of this publicity is good for SMIC and it certainly isn't instigated by them.

 

[eek2121]

I was discussing Zen 4. Not Zen 3. Zen 4's power can be cut with minimal to no loss in performance. Both Intel and AMD bumped their power specs this generation "just to compete". It's very telling when there's little loss in performance while cutting back significant power. In other worse they both pushed the power to gain scant performance. Ignore the power and Intel still needs more cores and more power. I'm not sure why this is difficult for some people to understand.

The 13900K locked at 253 watts still needs its 8+16 setup to match or just edge out the 7950X. It's a win for Intel, but it's a pyrrhic victory. Needing 24 cores against 16 while clocking higher just to match to beat AMD by a very small margin is not a good win.

No, you started off talking about Intel’s Fabs vs TSMC. Let’s keep things in context here. If Zen 4 were on N7, it would consume more power than Raptor Lake. Zen 4 230W -> Raptor Lake 253W is only 10% additional power.

Intel is a node behind. A problem that is being corrected starting a week or three from now.

They also need to work on better balancing their “P” core, but that is another argument.

 

[igor_kavinski]

I'm not entirely sure where you get the "one year" from.

Didn't read that they have been doing 14nm since 2019.

 

[SiliconFly]

Again, that is load of nonsense. Why not go along Your pseudo logic a bit further and shout "Zen4 is area INEFFICIENT, lets retire it in favour of Zen4C, a new pinnacle of efficiency on TSMC 5nm".
Oh wait, so now your core has actual requirement to clock 6ghz? What about other possible requirements like including full width AVX512? 1024bytes per clock from L1D? are they invalid cause You believe so?

You should mind your language. Or pls go and shout that nonsense to AMD yourself.

 

[A///]

No, you started off talking about Intel’s Fabs vs TSMC. Let’s keep things in context here. If Zen 4 were on N7, it would consume more power than Raptor Lake. Zen 4 230W -> Raptor Lake 253W is only 10% additional power.

I did, but I never mentioned a specific processor for Ryzen. Again, litho is one part of the equation. Poor design choice is poor design choice is poor design choice. To drive it further home, a poor design is a poor design and no advanced litho will save it.

 

[trivik12]

We will not see any other chip on N3B right. Would have been interesting to see Ryzen on it to see how far dense node could have helped in a non TDP constrained chip. We are unlikely to see N3E desktop before end of next year considering Apple will have 1st dibs for A18.

 

[moinmoin]

Would have been interesting to see Ryzen on it to see how far dense node could have helped in a non TDP constrained chip.

Not really. Density is always relaxed for high frequency designs. If only the TDP constrain is removed the chip's max achievable frequency would still be constrained by the density. This is also why having alternate density optimized cores makes sense, those increase density and efficiency at lower frequency at the cost of max achievable frequency. It's a trade off.

 

[maddie]

We will not see any other chip on N3B right. Would have been interesting to see Ryzen on it to see how far dense node could have helped in a non TDP constrained chip. We are unlikely to see N3E desktop before end of next year considering Apple will have 1st dibs for A18.

It's only about a 6% density difference between N3B and N3E. Versus N5, They are 1.7X & 1.6X for logic. Not exactly a huge difference.

 

[lightisgood]

TSMC Might Witness Significant Drop in Revenue For Upcoming Years Amid Manufacturing Concerns

TSMC's predicted revenue for upcoming years will drop amid concerns about wafer output and the company's plans to "delay" its manufacturing.

wccftech.com

GS predicts TSMC's catastrophe.
Surely TSMC N3 is ruined.

 

[DrMrLordX]

GS predicts TSMC's catastrophe.
Surely TSMC N3 is ruined.

How could you possibly derive that from the linked article? All Goldman Sachs is doing is translating the known decrease in N3B production into revenue predictions.

 

[dttprofessor]

INTEL4 is coming!

 

[DrMrLordX]

INTEL4 is coming!

Yay. Heavily-delayed and no major products left on it except for Meteor Lake, which itself has been constrained to mobile dice. Sorry, not excited for this one.

 

[Geddagod]

Isn't Intel 4 going to be the hardest jump Intel will have to do in their 5 node roadmap? I doubt Intel 20A is much of a density jump over Intel 3, though adding BSPD and GAAFET are major challenges (however BSPD is also getting derisked on Intel 3 internally), and Intel 3 and Intel 18A just seem like refinements over the previous "node".

 

[Henry swagger]

https://twitter.com/i/web/status/1704126470032114147

N3 looks terrible.. hope yields improve for arrow lake 🙄😐💻

 

[mikk]

TSMC 2nm delayed into 2026?

[Rumor] TSMC Taiwan, Baoshan fab construction plan has slowed down, and rumors are that TSMC’s 2nm mass production plan has been postponed to 2026.

https://twitter.com/i/web/status/1703748422723883349

Good news for Intel 18A if true.