Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

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Doug S

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Feb 8, 2020
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That article doesn't make sense. They say negotiation started with 3% and went to 6%, but Apple has rejected these offers? Who the heck would offer 3%, get rejected, and then say "OK how about 6%" :tearsofjoy: There's also no context given for what those prices are 3% or 6% higher than. The N5 price? The N3 price they told Apple six months ago?

So while they may be right there is some pricing dispute between TSMC and Apple, they obviously aren't right about the details.
 
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DrMrLordX

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Wait, Horse Creek is using DDR5? I don't see how that makes any sense economically. Am I missing something here? Like . . . DRAM soldered onto the board for lower cost, or something?
 

Doug S

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Wait, Horse Creek is using DDR5? I don't see how that makes any sense economically. Am I missing something here? Like . . . DRAM soldered onto the board for lower cost, or something?
Its a development platform not a real product.
 

jpiniero

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Oct 1, 2010
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That article doesn't make sense. They say negotiation started with 3% and went to 6%, but Apple has rejected these offers? Who the heck would offer 3%, get rejected, and then say "OK how about 6%" :tearsofjoy: There's also no context given for what those prices are 3% or 6% higher than. The N5 price? The N3 price they told Apple six months ago?

So while they may be right there is some pricing dispute between TSMC and Apple, they obviously aren't right about the details.
So I read the actual real article. The claim is that TSMC originally wanted to increase 6%-9% depending on the node. Apparently TSMC then dropped this to 3% for new nodes and 6% for 'mature' nodes. And Apple still rejected that.

It's possible that everyone other than Apple is going to have to pay the 6-9%.
 

Doug S

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I guess they'll need just one wafer to serve all existing developers. :p
I would bet it is really intended more for Intel's interal use and as a marketing tool than something they consider a viable product. They probably won't be selling this.

My thought is they will have a fairly fixed RISC-V design (i.e. don't look for those cores to iterate much if at all in successive process generations) surrounded with leading edge I/O and memory controllers they'll use in upcoming x86 CPUs and use it for validation of new processes - and those I/O blocks will be standard libraries available to foundry customers (and of course they'll be able to choose older stuff like PCIe 3 or 4, LPDDR4, etc. depending on their requirements and BOM target)

That way delays in new Intel core designs are completely decoupled from process validation cycles, plus this is something they can hand out to potential foundry customers without an NDA (at least not for the IP) to demonstrate how far along the new process is. I'm surprised it doesn't have a basic video output built in, I guess they figure it will be paired with a low end PCIe GPU (but that apparent lack provides further proof this is not intended as a real product)

Basically this would be the next step in process validation after the SRAM wafers Intel has always used for initial bootstrapping of a new process. These RISC-V wafers will show a process can handle a complex CPU, the latest I/O etc. so it is ready for x86 designs (i.e. chip design teams can't blame issues on process problems if the standard RISC-V SoC works) as well as customer designs. Using basically the same core in subsequent process generations would provide some high quality like for like PPA numbers. Kind of like the A72 or whatever core TSMC uses for its PPA comparisons between process generations.
 
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moinmoin

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And according to that slide Intel 3 will be the first publicly available leading edge node from IFS, not sure if that was that clear before.
 
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Exist50

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Everything 20a and below will require High-NA EUV as well.
When they said H2'24 for 18A earlier this year, they also indicated that they don't need high-NA for it or 20A.



One consequence of bringing in 18A, however, is that it means Intel is now definitely going into initial production of 18A without all of their High NA machines. 18A remains the process node where High NA machines will debut, but as the TWINSCAN EXE 5200 is still not expected to be in place until 2025, that means Intel will now have to use their existing 3000 series machines to kickstart 18A production. Until this latest development, Intel had been presenting High NA machines and 18A as being tied at the hip, so whether that was always the actual case or not, now that is clearly not the case.
 
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moinmoin

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Interesting development. Initially both foundries claimed with EUV they want to prevent going double pattering again as they excessively did with DUV.
 

DrMrLordX

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Apr 27, 2000
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When they said H2'24 for 18A earlier this year, they also indicated that they don't need high-NA for it or 20A.
Interesting. That's a change from earlier reports.

Interesting development. Initially both foundries claimed with EUV they want to prevent going double pattering again as they excessively did with DUV.
Could spell trouble. At least it isn't quad patterning.
 

LightningZ71

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In the end, if you want finer features, you either get machines that can draw them in one pass (High NA) or you use regular ones and multi-pattern (normal EUV). To my knowledge, there aren't many production level High NA machines out there in the market, so, multi-patterning is the name of the game for now...
 

DrMrLordX

Lifer
Apr 27, 2000
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In the end, if you want finer features, you either get machines that can draw them in one pass (High NA) or you use regular ones and multi-pattern (normal EUV). To my knowledge, there aren't many production level High NA machines out there in the market, so, multi-patterning is the name of the game for now...
The "old" story coming from the press/rumour mill was that Intel's next big shipments of EUV equipment would be High-NA machines arriving in 2024/2025. If those are delayed then it would change Intel's post-Intel 3 picture considerably.
 
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Doug S

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Interesting development. Initially both foundries claimed with EUV they want to prevent going double pattering again as they excessively did with DUV.

Did they ever claim it was to "prevent" double patterning, or was it about eliminating the huge and growing number double/quad patterning they were forced to do to keep DUV active? Going to double patterning on a few layers isn't the end of the world, and nowhere near the amount of multipatterning steps they were doing for e.g. TSMC's original N7 or what Intel must be doing for Intel 7.

If EUV had been further delayed we might be seeing 6 patterns at critical layers now. That is probably what Chinese foundries will be doing since they are limited to DUV. May not be remotely cost effective, but for "cost is no object" stuff like military gear or government funded supercomputers I'm sure we'll see it.

In the end it is all about cost, i.e. how much does it cost the foundry per KGD. Given how much more expensive high NA EUV scanners are than current EUV scanners all else being equal (i.e. if they could get as many "regular" EUV scanners as they wanted) doing a few double patterning steps might be the preferred option.
 

moinmoin

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Could spell trouble. At least it isn't quad patterning.
May still happen again.

Going to double patterning on a few layers isn't the end of the world, and nowhere near the amount of multipatterning steps they were doing for e.g. TSMC's original N7 or what Intel must be doing for Intel 7.
Of course it isn't the end of the world. It however is an interesting development that happens surprisingly early imo and may end off adding up over time. I get the impression some parts of the industry approach new technological "breakthroughs" as steps that make manufacturing easier from that point onward but they only turn out being harder and more complex with further development. In that sense double and quad pattering can become the lesser of two evils and get used again.
 

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