Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

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qmech

Junior Member
Jan 29, 2022
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So reduction of just 30mm2 in die area can result in a temperature hike of 30 degrees Celsius??? :-O

7 nm lithography process - WikiChip

If you (and other people on this forum) are right, why is WikiChip comparing Intel 4 to N7?
The WikiChip overview pages were made back when Intel called their Intel 4 process for "7nm". That's why it's in a section with N7 under the label "7nm lithography".

It has absolutely nothing to do with any other characteristic of the process.

If you want some insight from WikiChip into Intel 4, you could read the recent article on it:


From the conclusion:

On paper, those PPA characteristics positions the company’s new Intel 4 process at performance levels better than TSMC N3 and Samsung 3GAE. On the density front, Intel 4 appears highly competitive against N3 high-performance libraries.

....

With the Intel 4 process detailed in this article, the company’s ability to regain its leadership position in the semiconductor industry rests entirely on its execution.
 

Saylick

Golden Member
Sep 10, 2012
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Is TSMC's first generation of GAAFETs with front side power rails?
TSMC 14A ( second generation GAAFETs ) with buried power rails?
TSMC 10A ( third generation GAAFETs ) with PowerVia equivalent?
Very nice. If I remember correctly, their first take at N2 will just be to implement GAAFETs with BPD coming in a later, enhanced version. Slow and steady. We'll see if it lets them keep the lead, since Intel is pushing both GAAFETs and a more advanced version of BPD (via PowerVia) in the same commercially available node.
 

Doug S

Golden Member
Feb 8, 2020
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Very nice. If I remember correctly, their first take at N2 will just be to implement GAAFETs with BPD coming in a later, enhanced version. Slow and steady. We'll see if it lets them keep the lead, since Intel is pushing both GAAFETs and a more advanced version of BPD (via PowerVia) in the same commercially available node.
The same Intel that can't get any EUV chips out the door until next year, is suddenly going to race past everyone and and do that and implement a new transistor type and restructuring of the entire silicon stack in the next 24 months? Does anyone seriously believe that?
 

Saylick

Golden Member
Sep 10, 2012
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They're supposedly mitigating that risk by doing a PowerVia on a Finfet node ( which may serve as a backup plan? ) before moving doing PowerVia on 20A. Unlike 10nm where Intel tried to add too many new features all at once they'll do more incremental updates.
The same Intel that can't get any EUV chips out the door until next year, is suddenly going to race past everyone and and do that and implement a new transistor type and restructuring of the entire silicon stack in the next 24 months? Does anyone seriously believe that?
Yeah, Intel is being more cautious this time around by using an intermediate internal test node, although I think implementing GAAFETs first is the right move. BPD requires hybrid bonding two wafers together at the transistor layer, and who has more experience implementing bonding of dies than TSMC? Further more, their first stab at BPD is the lowest complexity variant: buried power rail, which apparently can be already implemented using today's tools. PowerVia has not been done before so Intel has to figure out essentially 3 innovations at once (GAAFET, hybrid bonding, and PowerVia) in order to take process leadership. Even if they do, I suspect it would only be short lived since TSMC just needs to get PowerVia working, at which it would be a smaller step for them at that point.
 

Doug S

Golden Member
Feb 8, 2020
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Yeah, Intel is being more cautious this time around by using an intermediate internal test node, although I think implementing GAAFETs first is the right move.

Doesn't everybody do that? Even when you plan on releasing two features together it makes sense to have separate teams solving their own problems independently. I don't know enough about the process steps to be sure, but I'm guessing that for test shuttles developing these features you might be able to skip some steps (especially during early development) if you have split them up and get results sooner than if you were trying to test both features at once on the same wafers.

TSMC seems to be taking a stepwise approach with GAAFETs themselves, first implementing them without any real density enhancement (or improvements in power routing) so they seem to think implementing GAAFETs without scaling (N2 reported as 1.1x) is worth splitting out. I would expect they will split up BPR and BSPD as well since one depends on the other. There is nothing requiring them to wait a year between releases if they have things ready earlier, or delivering features from both streams together (i.e. denser GAAFET libraries might come with an initial step in improved power routing) but we'll have to see about the timing.

While Intel may be doing internal nodes to reduce risk, by so publicly setting a goal of releasing everything in one big shot to try to retake process leadership they are setting themselves up for trouble. By marketing all these features together if they run into trouble the engineers are running the risk of encountering resistance from management to the truth and publicly admitting yet another failure to deliver. They'd be forced to either delay the whole node to wait for the missing features to catch up, or release without everything that has long been promised. The pressure on process engineering will be immense to make the whole enchilada arrive as promised, even if yields are terrible and management tells them "we'll just accept poor yields for now and fix it in production" rather than admit anything is wrong. I mean, look at how long they denied the truth about 10nm?

So even if the day approaches when Intel says they will begin shipping CPUs on this new node and claims everything on is on track I will STILL be skeptical it will really happen in true production quantities.
 

jpiniero

Lifer
Oct 1, 2010
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The same Intel that can't get any EUV chips out the door until next year, is suddenly going to race past everyone and and do that and implement a new transistor type and restructuring of the entire silicon stack in the next 24 months? Does anyone seriously believe that?
The two products that have been linked to 7 nm - Meteor Lake and Granite Rapids - is just a tile filled with CPU cores. The rest (ie: the majority) of the product is either fabbed at TSMC or 22FFL.

But since the tile is just the cores, presumably the design is very salvageable. In theory (heh) as long as there's enough not busted Cores on a tile, they could sell it. It's not like their current chips where a defect in large portions of the die means the trash bin. I think that's what the strategy is. They are basically going to sell pre-pre-pre risk production level chips and whatever they get is whatever they get. And if that's only 1+4 or even 0+4 for Meteor Lake that's what they'll sell.
 

Exist50

Golden Member
Aug 18, 2016
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Hopefully that won't comprise the entire Meteor Lake lineup! Nobody needs another Cannonlake.
Yeah, if things were that bad, it's effectively a new Cannonlake, and would never really ship. But everything I hear about Intel 4 indicates it's not that bad. Or people underestimate exactly how terrible Cannonlake was.
 

Doug S

Golden Member
Feb 8, 2020
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The two products that have been linked to 7 nm - Meteor Lake and Granite Rapids - is just a tile filled with CPU cores. The rest (ie: the majority) of the product is either fabbed at TSMC or 22FFL.

OK but is Intel doing that because it is cheaper/better, or are they using other processes for "the majority of the product" due to capacity constraints?
 

RTX

Member
Nov 5, 2020
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Will there always be an internal node before an IFS node for testing purposes? Intel 4 and 20A -> Intel 3 and 18A etc

16A ( internal use only? ) and 14A ( IFS? )
 

Doug S

Golden Member
Feb 8, 2020
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More articles stating Apple will be using N3E for A17 and M3, now saying they have multiple sources confirming this. Between that and the claims N3 will have relatively few wafer starts when it begins 'mass' production (perhaps already begun) for customer shipments in early 2023, it looks like we can consider N3E the 'real' N3, and Q2 2023 its 'real' mass production start.

Assuming the Pro/non-Pro split on iPhone 14 wasn't a one-off due to the cost of LPDDR5, there will likely be a more noticeable performance gap between the two options with iPhone 15.
 

jpiniero

Lifer
Oct 1, 2010
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More articles stating Apple will be using N3E for A17 and M3, now saying they have multiple sources confirming this. Between that and the claims N3 will have relatively few wafer starts when it begins 'mass' production (perhaps already begun) for customer shipments in early 2023, it looks like we can consider N3E the 'real' N3, and Q2 2023 its 'real' mass production start.
This directly contradicts what TSMC is saying. The only thing that would be plausible would be an low volume product like a super expensive iPhone Ultra which gets the A17 and the rest get the A16.
 

Doug S

Golden Member
Feb 8, 2020
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This directly contradicts what TSMC is saying. The only thing that would be plausible would be an low volume product like a super expensive iPhone Ultra which gets the A17 and the rest get the A16.
Well we'll have to see what TSMC has to say in coming months, but Apple could potentially use risk production volume to serve their needs given the yields TSMC recently reported for N3E compared to N5 in a similar pre-risk production stage. A17 and M1 aren't overly large dies, and Apple does bin a little bit these days so the odd bad core doesn't hurt them.

I was skeptical when it was first reported, but now that it is being reported as confirmed by multiple sources I think our interpretation of TSMC's public statements may need to re-evaluated.
 

jpiniero

Lifer
Oct 1, 2010
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They could do it if say TSMC started at the beginning of Q3 and the iPhones that had it were made available in November. But even that would have to be a low volume model I think.
 

DrMrLordX

Lifer
Apr 27, 2000
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Could Nvidia use Intel 4 for a 4000 Super generation? It's roughly the same density as N4 HD at 125mTr vs 123 mTr.
Is Intel even offering that node through their foundry service? And can they drive the volumes that nVidia would need while also producing enough Meteor Lake tiles?

Can Intel fab dGPU dice that large on Intel 4?
 

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