Ajay
Lifer
- Jan 8, 2001
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There have been recent developments in ultra thin dielectric like TiN and TaN that are around 2 A in thickness (Plasma nitrided deposition). Exactly what is going to end up in the next gen GAA xtors is hard to find out - secret sauce and all that. Bringing poly-silicon down to those dimensions is a different story. The great difficulty in moving to more advanced nodes is exemplified in in building up transistors from such thin structures with exacting uniformity and reliability under dynamic thermal loads. No wonder node development is getting pushed back by various Fabs and are facing serious yield problems. Oh, and let’s not forget the in-process metrology problems associated with these ever shrinking transistors and metal channels.
The reason they no longer represent transistor dimensions is because transistors started being made differently. Everyone continued with the same node naming to reflect the ~2x increases in transistor densities every couple years as Moore's Law plugged on. You had to call it something, so if you previously had a node "x nm" that reflected actual gate width and you got a doubling of transistor density every two years by shrinking the gate by .7x, after you started making transistors differently it made sense to keep calling a new node ".7x nm" even if that no longer reflected physical transistor dimensions.
Lately we've been seeing less than 2x gains in transistor densities - i.e. TSMC's N5 was 1.8x as dense as N7, and N3 1.7x as dense as N5, and for cache the gains were much less. That's probably why they took the step to stop using "nanometers" at all in their process naming.
As transistor designs go more vertical, they'll be able to continue making more of them fit in a given sq mm of a chip. Beyond that there is already discussion of stacking multiple transistors on top of one another, at least for simpler structures like cache, and backside power delivery will free up routing issues that act to restrict how dense your transistors can be (i.e. wiring is starting to become a limitation on density, not the size of the transistors themselves)
Thanks for the explanation, i think ive heard some of that before but synthesizing it into actual comprehension i think is still elusive 😂
With respect to actual "feature size", regardless of transistor pitch (or whatever the metric is), how small are cutting edge lithographic techniques able to fabricate? The idea of even being in range (say smaller than 20 nm) of atomic scale is completely mind-boggling to me.
With respect to actual "feature size", regardless of transistor pitch (or whatever the metric is), how small are cutting edge lithographic techniques able to fabricate? The idea of even being in range (say smaller than 20 nm) of atomic scale is completely mind-boggling to me.
Node names don't have a correlation with transistor densities but transistors do have some physical dimensions in the 'patently ludicrous' dimension with fin widths being around 7nm since the 14nm FinFET. The fin width on N3 is probably still around 6 nm for physical strength. The fin and GAA technology 'quantizes' the amount of current per fin or 'wire' in a transistor so as one fin dimension gets smaller another dimension will get bigger. The fin width is extremely narrow but the height of the fin keeps increasing in successive nodes with fin depopulation. Line edge roughness or fin width is an issue as some missing atoms changes the current capacity of the fin and affects parametric yeild.
Here is an article about the ability to selectively thin fins and about improving line edge roughness.
Selective Removal For Stronger Fins
Trim fins after dummy gate removal to improve PPAC and reduce deformation.
semiengineering.com
"In our recent paper we demonstrated the feasibility of this scheme with precise etch control and even improved line edge roughness of the silicon fin (LER 2.1nm pre, 1.8nm post)."
You will note that they are improving line edge roughness on the fins to 1.8 nm or 18A. For Intel's 18A node the fins will be laid on their sides and the thickness of a horizontal 'ribbonFET' will be an interesting measurement and I will speculate it will still be around 5-7nm thick.
Couple interesting things I noticed over the weekend. New IMEC roadmap through "A2" (0.2 nm) in 2036. We're already off that train since TSMC is indicating N2 in 2025, but they've got proposed transistor designs (starting to look like little skyscrapers) to continue scaling for a half dozen nodes beyond N2 so that should keep Moore's Law in business for a while.
The second was a Gartner list showing the relative output of leading foundries at different processes. Just to show how much revenue there is still is from TSMC and others in two decade old "obsolete" process nodes like 130/180 nm.
The second was a Gartner list showing the relative output of leading foundries at different processes. Just to show how much revenue there is still is from TSMC and others in two decade old "obsolete" process nodes like 130/180 nm.
Yes but it is “inconsistently” correlated and thus you starting having human perception errors for it is too inconsistent. Trying to use a name to reduce complexity into two syllables is a fetish, it leads to nonsense.
This is not new though, it is at least 10 years old now. Arguably much older.
IntelUser2000
Elite Member
- Oct 14, 2003
- 8,183
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The past 3 CEOs of Intel were focused on cost-cutting, and part of the reason why they lost process leadership starting with 14nm.
Ah yea plan on the most ambitious process(10nm) ever while firing experienced employees and cutting costs. Sure that'll work great.
First thing Otellini did was firing over 10K employees. Cost was also the reason why he didn't go for making the iPhone chip. For all the good things he did, he made some very critical mistakes.
Of course we can't forget about Brian Kraznich. He's the one that instituted "no hiring former employees" policy that recent articles are talking about(and just revoked) Things like that were done purely out of spite, and to keep 100% loyalty which is absolutely ridiculous.
Bob Swan continued the cost-cutting but at least an improvement.
Intel Museum: Journey Through Decades of Innovation
Explore the people and technology that changed our world through Intel Museum online exhibits, and view event, location, and tour information.
www.intel.com
Intel is not proud of him as he is mentioned only in passing in their timeline of events. I guess the whole "he broke our rules" firing was just an excuse to get rid of him.
IntelUser2000
Elite Member
- Oct 14, 2003
- 8,183
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Of course it is. The stock was doing well(due to excessive cost cutting and stock buybacks) so he couldn't technically be fired.
Always have to read between the lines. Especially among folks like these that will never admit their wrongdoings.
The board can always vote to fire someone, but it spooks shareholders less to say, "He was violating company policy" than "He's setting up the company for ruin".
DrMrLordX
Lifer
- Apr 27, 2000
- 19,366
- 8,149
- 136
It's awfully convenient for Intel that he boinked a subordinate years ago.
Companies will look the other way on that if the performance is there...see kevin sharer.
Ajay
Lifer
- Jan 8, 2001
- 11,423
- 5,177
- 136
above poster has been fairly reliable. It appears Apple will move to N4X next year. It means we have to wait until 2024 for N3 in mass manufactured products. May be Mediatek would be the 1st one again in small volume or even Intel for say ARL gfx tiles.
I'd be surprised if Apple skips N3 for the A17, especially given the rumor of an N3E pull-in. N4X seems more useful for the Mac chips.
The announcement of N4X doesn't mean N3 won't be available next year. Apple cares more about power consumption than they do about performance. I don't see them ever using a performance focused process given that the vast majority of Mac sales are laptops. They absolutely will use N3 for phones, there is less than zero chance they use N4X for A17.
Theoretically they could use N4X for something like M1 Max (and its multi SoC big brothers) but I would bet strongly against that. It would blow the neat way they designed the M1 Pro & Max in tandem (as a "chop")
anandtech reported that N3E is a 2024 HVM product. So how can Apple use that for A17. May be they will go with N3 instead.
www.anandtech.com
TSMC Roadmap Update: N3E in 2024, N2 in 2026, Major Changes Incoming
anandtech reported that N3E is a 2024 HVM product. So how can Apple use that for A17. May be they will go with N3 instead.
TSMC Roadmap Update: N3E in 2024, N2 in 2026, Major Changes Incoming
It was already scheduled for H2'23. If they can successfully pull it in to Q2, as the rumor suggests, that would be early enough for Apple. Surely they're at least going to try.
If N3E isn't pulled in enough for them to use, they'll use N3 (i.e. the "fixed" version some are calling N3b that starts mass production in Q4 this year)
From the rumors about N3E it sounds like it may get pulled in enough - especially if you consider "risk" production on a node tweak is not all that risky so they could build up a supply using that even before it officially entered mass production.
N4X doesn't seem like an Apple move at all. Their chips are fast enough across the range that porting everything to a new node just for desktop chips would be silly. N4X is definitely for AMD and Nvidia, maybe Intel if they're still that far behind. So we'll be seeing like, CDNA4 on N4X, maybe some sort of HPC version of Zen4 and whatever AI accelerator version Nvidia comes up with next.
Apple is almost certainly aiming for N3E next year, it wouldn't be entirely surprising if TSMC's schedule bump is due in part to getting Apple onto production schedule. Wouldn't be surprised if this years A series (what's the number at now?) was just an N4P version of last years due to N3 getting delayed, and that's why there's not much change there.
Sounds too risky to me. Have to think they will go with N4 or some variant for the 23 iPhone.
Why does that sound risky? TSMC is starting N3 production in Q4 this year, six months ahead of the usual window (i.e. normally they'd use something that entered mass production in Q2 2023 in the fall 2023 iPhone)
This is from WSJ article that we are hitting Supply issues on leading edge. Probably will impact everyone but Apple is the least likely to be impacted as they get the 1st bite of all leading edge nodes. This could be why I could see 3nm missing until 2024.
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