I reckon you will see a full cycle of Raptor Lake, and then after that... that's where Arrow Lake on TSMC N3 would have made sense.
Saylick
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Had some spare time so I did some memory jogging on the number of EUV layers each modern node uses:
- Intel 4: Up to 12 layers, but possibly 13 layers.
- TSMC N5: About 14 to 15 layers.
- TSMC N3: Originally about 25 layers, reduced down to 20 for cost and HVM.
- Intel 4: Up to 12 layers, but possibly 13 layers.
- TSMC N5: About 14 to 15 layers.
- TSMC N3: Originally about 25 layers, reduced down to 20 for cost and HVM.
Uh, you are full of it. Intel has more than enough EUV equipment. We've established this already. Intel can push out 110-120k wafers per month.I got to stay on top of this stuff as an AMD investor, ya know?
If I had to guess, Intel today has about 10-20 EUV machines vs. TSMC having like 60-80 machines. It's possible 10-20 EUV machines are enough just to supply Intel for their own Intel 4 demand, but it will be dependent on yields and the number of EUV layers Intel 4 uses. TSMC has years of EUV experience ahead of Intel: TSMC has shipped N5 in high volume for over a year now, while Intel hasn't even rolled out an EUV node for HVM. The small quantity of Intel 4 for Meteorlake mobile is probably just risk manufacturing, i.e. just to get some out to say they're shipping an EUV node for PR reasons. Dylan is right in that the next critical step, which is figuring out how to ramp to high-volumes, will be crucial. If Intel can't figure that out, it won't matter how many EUV machines they have because they wouldn't be leveraging them to their best potential.
The article above specifically relates to IFS. Intel can easily pump out their own chips on EUV, but if they ONLY do that, they will be seen as treating IFS as a 'second class citizen'. They need EUV not just for their stuff, but for the other folks as well.
There is a possibility AMD could even use IFS at some point in the future. It will all come down to dollars and cents.
Saylick
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What's your source for Intel being able to push out 110-120k wafers per month? Is that on a node that uses EUV? If so, how many layers? TSMC was reported at a production output of 55k-60k wafer starts per month back in 2021, and they planned on doubling that to serve all of their customers at the end of 2021. Are you telling me that Intel can somehow magically match TSMC's EUV output with a fraction of the EUV machines?
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They need EUV mainly for the Fin + Poly and couple of metal layers e.g. M0 to M3 max.
The EUV usage simply reduces multi patterning but DUV should be capable of handling most of the metal layers.
Each of the actual chip layers needs multiple lithographic layers which is between 60 and 75 for N5 for example and depends how many metal layers are there on the device.
But still, TSMC and Samsung have the captured almost all the installed base of EUV machines.
Situation may change if US/EU Govt start influencing ASML. Otherwise TSMC and Samsung have deeper pockets than Intel when it comes to a bidding war.
No point debating politics here, but TSMC making a fab in Japan has more than one aspect to it. They want uninterrupted access to the etching equipment, photoresist, chemicals etc., (which at the moment is dominated by multiple Japanese firms) and engagement with
Dylan has good articles on these.
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But in other news TSMC raised N5 wpm to 150K
This is not unexpected, because F18P4 was supposed to also contribute to N5 family.
So they did indeed manage to raise F18P1/2/3/4 to around 40K wpm each as planned.
I guess with the slight push back of N3, F18P5/6/7/8 can focus on N3 instead of using P4 for N3.
台積電5/4奈米大單噴發上調出貨 HPC三雄超前預訂3/2奈米產能
台積電全線產能滿載，5奈米製程更是供不應求。據半導體設備業者表示，台積電近期調升單月出貨量，逐步由現有約12萬片，至第3季時將達15萬片。
www.digitimes.com.tw
This is not unexpected, because F18P4 was supposed to also contribute to N5 family.
So they did indeed manage to raise F18P1/2/3/4 to around 40K wpm each as planned.
I guess with the slight push back of N3, F18P5/6/7/8 can focus on N3 instead of using P4 for N3.
What is AMD gonna get out of this? Wouldn't they have to create a separate die compatible with IFS's processes?
So NVIDIA Hopper GH100... 814 mm² on TSMC 4N. It looks like huge dies (and the TSMC N5 process family) are still alive and well.
And not to dredge this up again, but Intel being constrained on EUV equipment for all of their recently announced fab expansions is obviously going to be a thing, but it has very little to do with Intel 4 or any products Intel plans on shipping in the next two years. Fab D1X Mod 3 in Hillsboro, OR will come online this year (first tool rolled in Aug 2021), and Fab 34 in Leixlip, Ireland will follow next year (first tool rolled in Jan 2022). Those are your Intel 4 fabs, and Intel already has the tools to fill them.
Fabs 52 and 62 in Chandler, AZ are next in line and destined for IFS and Intel 20A, but Intel only broke ground on those 6 months ago. Although the Fab 28 expansion in Kiryat Gat, Israel might be done before those are, seeing as the first phase was underway by May 2021. By piling on two new fabs in New Albany, OH by the end of 2025 and two more in Magdeburg, Germany by the end of 2027, Intel will obviously need to up their EUV equipment orders beyond what they had already committed to for their existing manufacturing footprint. That will put pressure on ASML, but honestly, the narrative that Intel is in trouble because they didn't order as many machines as TSMC and Samsung is ridiculous. Intel is much smaller, only recently started taking on foundry customers, and they won't face any shortage until they can get a process that requires EUV to HVM and enough products taped out on that process to actually utilize the capacity they have.
And not to dredge this up again, but Intel being constrained on EUV equipment for all of their recently announced fab expansions is obviously going to be a thing, but it has very little to do with Intel 4 or any products Intel plans on shipping in the next two years. Fab D1X Mod 3 in Hillsboro, OR will come online this year (first tool rolled in Aug 2021), and Fab 34 in Leixlip, Ireland will follow next year (first tool rolled in Jan 2022). Those are your Intel 4 fabs, and Intel already has the tools to fill them.
Fabs 52 and 62 in Chandler, AZ are next in line and destined for IFS and Intel 20A, but Intel only broke ground on those 6 months ago. Although the Fab 28 expansion in Kiryat Gat, Israel might be done before those are, seeing as the first phase was underway by May 2021. By piling on two new fabs in New Albany, OH by the end of 2025 and two more in Magdeburg, Germany by the end of 2027, Intel will obviously need to up their EUV equipment orders beyond what they had already committed to for their existing manufacturing footprint. That will put pressure on ASML, but honestly, the narrative that Intel is in trouble because they didn't order as many machines as TSMC and Samsung is ridiculous. Intel is much smaller, only recently started taking on foundry customers, and they won't face any shortage until they can get a process that requires EUV to HVM and enough products taped out on that process to actually utilize the capacity they have.
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It isn't like they're talking about going there tomorrow, and at this stage it is most likely due diligence. They want to see what Intel's roadmap is like, what sort of pricing there will be, and so on. Even someone like Apple even more committed to TSMC than AMD will be talking to Intel, so if nothing else TSMC knows there is now some competition.
It would make sense though for AMD & Apple to send a little something Intel's way to drive the point home. It could be done with something less critical than iPhone or Apple Silicon SoCs, i.e. they could have them fab an upcoming Watch SoC, or maybe some modems, since those will be discrete at least the first couple generations. AMD could throw them one of their lower end / more mainstream GPUs, the kind of thing they might use GF or Samsung now anyway.
I'm curious as to why TSMC and Samsung are considered to have 'deeper pockets' than Intel? From TSMC's Q4 2021 earnings, their net revenue in 2021 was $56.822B USD, net income $21.372B USD. The entirety of Samsung meanwhile recorded sales of about $228B USD for a net profit of around $32.5B USD. (Samsung semiconductor was probably responsible for around $18.4B USD of the net profit.) Meanwhile Intel reported revenue of $79B USD and net income of $19.9B.
Now there is a bit more of a difference in reported cash on hand. With Intel somewhere around $28B USD compared to TSMC's $38B USD and Samsung still being somewhere around $100B USD. So in that respect it would make a bit more sense?
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See post below, with few extracts on record cap expenditures in semi industry
No one has beaten Samsung for close to two decades barring one year in 2009.
If you read TSMC's earnings report official committed cap expenditure is 44 Billions USD in 22 alone.
But before you need the EUV equipment, fabs are need and customers needed. And TSMC's customers bankroll fab expansion. TSMC's customers have deep pockets. (Apple et al )
Samsung numbers are for their entire semiconductor operation including memory and NAND. Hence it's of little surprise that they've been on top given that Micron and SK Hynix have each been at around $10B USD per year capex I believe?
There's no question that TSMC has considerably ramped up their capex in 2021 and plans to continue that trajectory in 2022. Quick search implies that their capex from 2017 to 2020 was something like $12B, $11B, $17B, $18B. Which isn't that far off of Intel's $12B, $15B, $16B, $14B. It's the 2021 and projected 2022 numbers (and to a lesser extent 2020) where Intel is coming in at around 2/3 of TSMC's capex. Though one point of note there is that I believe Intel's capex is always on their leading edge node while 70-80% of TSMCs capex goes toward leading edge?
One other question - have either TSMC or Samsung committed to building a leading edge fab outside their respective home countries? I know the existing Samsung Austin fab was one of their initial deployments of 14nm, and that may well still be the process node it's on currently? Would definitely be interested if anyone has seen anything other than speculation as to whether the new Samsung fab is going to be their 3nm process. By comparison we know that TSMC's Arizona facility is slated for their N5 process in 2024, correct?
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TSMC's Capex is almost fully process development, packaging and fabs, they don't spend on anything else., Can't say the same for others.
Yeah both TSMC and Samsung are expanding outside their home countries.
Samsung is building another fab in same location in Austin and TSMC F21 is being built in Arizona, actually they will bring it to same level as F18P4+ and in 4 phases despite initial plans on the contrary.
TSMC is building a fab in Japan,
If not for sanctions both of them want to make fabs in China. Actually started but suspended.
EU fab for TSMC and Samsung will likely be announced as well.
But regarding EUV machines, like I said, the machines are needed for few layers only it will be enough if not in surplus.
Nikon latest machine is reported to be capable of 5nm without EUV using new high precision multi patterning capability, and by 2025 they will have some thing new too.
Reportedly taking over ASML customers in China on a massive scale.
Japanese companies are the ones to watch out for if you invest in this field. Photoresist, lasers, etching tech, pellicles, etc.
DrMrLordX
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uzzi38
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Also might be worth noting that N3E uses 4 less EUV layers than N3 again to reduce cost.
Saylick
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uzzi38
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I'd think 16 based off of this:
It's quite new information, I'd assume it's 4 less layers than N3 as it's known now.
It's a good thing to be able to keep the layer count down, assuming the metrics are the same.
JasonLD
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Moore's what ? Law ? Please can we move past this non existent '"law"' ? Thanks.
The final node before a major change (like aluminum to copper, planar to FinFET, DUV to EUV) is more likely to see less impressive metrics. After all, why implement such changes if they were able to keep going at the previous pace without?
As N3/N3e is the last FinFET node for TSMC, seeing less of an improvement than previously is perhaps not surprising. They appear to have decided in hindsight they tried to push things just a bit too far with their initial N3. Apple was surely unhappy with the schedule slip, since they would have hoped to be able to use N3 this fall, even if it was a bit more expensive than planned. Most of TSMC's other big customers cared less about the schedule (since they weren't getting first crack at N3 anyway) but the price was a bigger issue for them.
The timing of N3e looks like it should work for Apple next year, so TSMC will keep them happy, and it will be cheaper so they'll also keep their other big customers happy. Yeah, not quite as good as the original N3 or the "N3P" they might have originally penciled in for next year on internal roadmaps, but if rumors about N2 looking really good and entering risk production on schedule next year are true, they might get back on the yearly Q2 mass production train. Of course, there is another transition around the corner, to high NA EUV which even though it'll be far less disruptive than the DUV->EUV transition will halve the size of the reticle which is forcing Intel and Nvidia's hand whether or not they wanted to go the chiplet route.
As N3/N3e is the last FinFET node for TSMC, seeing less of an improvement than previously is perhaps not surprising. They appear to have decided in hindsight they tried to push things just a bit too far with their initial N3. Apple was surely unhappy with the schedule slip, since they would have hoped to be able to use N3 this fall, even if it was a bit more expensive than planned. Most of TSMC's other big customers cared less about the schedule (since they weren't getting first crack at N3 anyway) but the price was a bigger issue for them.
The timing of N3e looks like it should work for Apple next year, so TSMC will keep them happy, and it will be cheaper so they'll also keep their other big customers happy. Yeah, not quite as good as the original N3 or the "N3P" they might have originally penciled in for next year on internal roadmaps, but if rumors about N2 looking really good and entering risk production on schedule next year are true, they might get back on the yearly Q2 mass production train. Of course, there is another transition around the corner, to high NA EUV which even though it'll be far less disruptive than the DUV->EUV transition will halve the size of the reticle which is forcing Intel and Nvidia's hand whether or not they wanted to go the chiplet route.
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