Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

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DisEnchantment

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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

1587737990547.png
N7 performance is more or less understood.
1587739093721.png

This year and next year TSMC is mainly increasing capacity to meet demands.

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.


1587739615344.png

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.
 

DrMrLordX

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This is a bit surprising tho. Wonder if Intel 20/18A's density jump over Intel 4/Intel 3 is really that bad.

It shouldn't be surprising. Alarm bells should have been going off in peoples' heads when Intel announced that they were making 20a and 18a EUV rather than High NA EUV nodes.
 

DavidC1

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Intel 3 HD cells are around the same density as TSMC N4 HD cells lmao
They might be what they mean in their slide that Mobile optimization only happens on 18A-P and 14A. They continue their transistor drive current leadership at the cost of density, and low power performance.

Look at 22nm for example. Based on the naming it should be TSMC 20nm in density but in reality it was like this:
-TSMC 28nm was only 30% larger than Intel 22nm. Meaning Intel 22nm was 50% larger than TSMC 20nm.
-Intel always had a transistor performance lead, and it wasn't small. For example, the aluminum interconnect Intel 0.18u was 30% better than AMD's copper infused 0.18u.
-Intel also had a 1 year lead in TTM, which is a big thing too.

So for 18A being "leadership" applies in that for their own product which was also ingrained with multi-decades long focus on clock speed, is advantageous. But when it comes to shifting trends(even for their own) and foundry ambitions, it's not so clear.
 
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SiliconFly

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Another interesting find, Just connecting the dots...

Don Soltis (Senior principal engineer and chief architect for Xeon Efficient-core) said last year that Sierra Forest (Intel 3) has 100 billion transistors (approx).

Wild_C on twitter said last year that Sierra Forest (144) has a die area of 578 mm2 (approx).

With this we can directly calculate Sierra Forest on Intel 3 HD cell density at 173 MTr/mm2 (approx).

(Note: 100B transistors has to be 144 and cannot be 288, cos with 288, we arrive at 86.5 which is way below Intel 3 HP cell density itself which is totally wrong. So, 100B has to be 144 only.)

This puts Intel 3 HD (theoretical) peak density at least at 180 MTr/mm2 (approx).

Another key observation is:

HP:HD cell ratio for Intel 14 is 1:1.53, Intel 7 is 1:1.5, TSMC N7 is 1:1.4, N5 is 1:1.48, N3 is around 1.59 i think. The industry average is around 1:1.5. If we apply this to Intel 3, we arrive at ~200 MTr/mm2 (approx). Even assuming worst case and adjusting the ratio to paltry 1.3 for bigger than expected HD cell height, it'll still be ~175 MTr/mm2, which tracks well with Don Soltis+Wild_C numbers.

This puts Intel 3 very near TSMC N3.
 
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Geddagod

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~150 MTr/mm2 is completely wrong (as discussed with witeken). Problem is he doesn't understand. His estimate is way off!

TSMC N3 HP density is 124 MTr/mm2. Intel 3 HP density is 135.74 MTr/mm2. Intel 3 HP density is higher than TSMC N3 by 10%.

And when it comes to HD, TSMC N3 is around 200 MTr/mm2.

So, basically what you are trying to say is:
When TSMC N3 HP is only 124, its HD is ~200.
And when Intel 3 HP is already 136, its HD is only a meager 150???

Your math is wrong.
Intel 4 is 0.6 x 4/ (150 x 240) + 0.4 x 32/ (950 x 240) = ~122.8 MTr, Intel 3 is 0.6 x 4/ (150 x 210) + 0.4 x 32/(950 x 210) = ~140.35
Math looks like it checks out? Witeken said 150, maybe I missed a scaling factor, idk.
So why does TSMC scale so much better than Intel from HP to HD?
TSMC N3 this time around is using finflex- and that's where the HD figure of ~215MTr/mm2 comes from (with the 48nm CGP as well IIRC). The 2-1 variant. The HP cells, however, is still being compared to the 3-3 variants, and that's with the relaxed 54nm CPP figure as well.
TSMC N3 HD vs HP ratio this time around is ~1.73. TSMC N5 HD vs HP was 1.48. That is a significant difference.
Ok, so what's wrong using the 1.5x scaling figure for Intel then that N5 enjoys?
Well, the cell height scaling is quite simply worse. TSMC N5 HD cell height is 210nm, which is the exact same as the cell height of Intel 3 HD.
1713890854609.png
TSMC's HP cell height is quite high on the other hand, is:
1713890956081.png
(angstronomics 5nm article)
So what makes Intel 4 HP so dense?
Intel 4's Cell Height is quite low.
1713891217592.png
If you look at this, you see that Intel 4 CPP isn't anything that amazing. It's between N5 and N3, an closer to N5 to boot. However its height is literally lower than even N3, and by a decent amount too.
So why doesn't Intel 3 cell height scale better when lowering the fin count?
Well, who knows. Maybe the track count just can't scale much lower, since Intel 4's HP metal track count is already impressively low (at 5.33 vs 9 for N3 and N5).
1713894453941.png
Maybe N5's fin pitch is larger than Intel 4's, which provides it better scaling as you remove fins. Idk.

Regardless, the numbers are right there. Intel themselves claimed a cell height of 210nm for their HD libs, and N5 HD lib cell height is also 210nm. The only thing that's making Intel 4 denser now is the slightly lower CGP of 51 vs 50nm. And for Mark Bohr's calculation, those 2 numbers are pretty much all that matter *** with some asterisks that are described in angstranomics article.

The only thing that can "save" Intel 3's density now is the shrinking of CGP even lower, which wouldn't be new from Intel (Intel 7 had 60/54 nm CGP variants IIRC) but seeing how it's not listed in the abstract while all the other major points are, I doubt it.
As far as I understand the jump from Intel 4/3 to Intel 20/18A is less about any density increase and more about decreasing cost, increasing yield and significantly higher volume. Intel 4/3 are the last nodes in an unsustainable development of internal first/only nodes whereas Intel 20/18A are the first ones that should make IF actually competitive in the market.
TBH I was also expecting a shrink so it would be more competitive against N3, but who knows ¯\_(ツ)_/¯
I'm always pretty much optimistic for Intel... for the first couple months of the rumor mill
Like shown in the video (and discussed in the other thread), I too remember reading that FinFlex is actually a part of N3B itself. So, N3E is definitely going to have some slight regression after all.
N3E has finflex
They might be what they mean in their slide that Mobile optimization only happens on 18A-P and 14A. They continue their transistor drive current leadership at the cost of density, and low power performance.
Based on that rumor of Intel 18A "high density" cells only being marginally more dense than N5 HD cells, I wonder if that's actually due to them not shrinking cell height/cpp or them just not offering a lower amount of fins until something like 18A-P or 14A. That's my copium at least lol.
But ye I agree, I think intel is laser focused on perf/watt (prob perf/watt specifically for HPC too).

Another interesting find, Just connecting the dots...

Don Soltis (Senior principal engineer and chief architect for Xeon Efficient-core) said last year that Sierra Forest (Intel 3) has 100 billion transistors (approx).

Wild_C on twitter said last year that Sierra Forest (144) has a die area of 578 mm2 (approx).

With this we can directly calculate Sierra Forest on Intel 3 HD cell density at 173 MTr/mm2 (approx).

(Note: 100B transistors has to be 144 and cannot be 288, cos with 288, we arrive at 86.5 which is way below Intel 3 HP cell density itself which is totally wrong. So, 100B has to be 144 only.)

This puts Intel 3 HD (theoretical) peak density at least at 180 MTr/mm2 (approx).

Another key observation is:

HP:HD cell ratio for Intel 14 is 1:1.53, Intel 7 is 1:1.5, TSMC N7 is 1:1.4, N5 is 1:1.48, N3 is around 1.59 i think. The industry average is around 1:1.5. If we apply this to Intel 3, we arrive at ~200 MTr/mm2 (approx). Even assuming worst case and adjusting the ratio to paltry 1.3 for bigger than expected HD cell height, it'll still be ~175 MTr/mm2, which tracks well with Don Soltis+Wild_C numbers.

This puts Intel 3 very near TSMC N3.
SRF is built on both Intel 3 and Intel 7. Without the breakdown of the transistors in the IO vs Compute tiles, the total transistor count figure isn't that helpful for determining the density of Intel 3 itself.
100B transistors has to be 288, cos with 288, we arrive at 86.5, which makes sense. The real density of these server chips should be way below their theoretical density.
Looking at the real density of small mobile chips and seeing how they lineup against server chips is not the play. It's not the area that's the problem, but the completely different ratios of cores/cache/io, and also the iGPU, which is typically made of pretty dense logic (which can provide a decent boost in numbers).
I'm guessing you saw this chart and decided to try this:
1713893698230.png

We can go ahead and look at an example of this not working for server chips. SPR, on Intel 7, has a density of ~30 Mtr/mm2. What's Intel 7's UHP lib density? ~60MTr/mm2. The ratio there is like 50%. But what if we apply this to GNR since the server to logic density ratio looks to be 1/2? This would mean Intel 3 (using the 288C SRF model) could be estimated to be ~170 MTr.... wait a second....
checks twitter
are you literally not counting the IO tile area... at all? Wth!
So lets pretend that Intel 3 vs Intel 7 IO scaling is 2x. I doubt it's that high, but whatever. Let's cut the area of the IO tiles in half now, add in the 2 compute tiles, an area of ~1397 mm2, 100 billion transistors, gives u a density of ~72, which is roughly half of Intel 3's HD lib density of ~140.

Except all this math is bad, because it's never this simple, and we made way too many assumptions on the way. EMR has a transistor density of ~40 MTr. Does this mean Intel's 7 UHP lib density increased to ~80 MTr/mm2? What about ICL server, with its horrendous transistor density? Mixing in compute and IO tiles too, or just ignoring the IO tiles completely....

I think this exercise was a bit pointless tbh. Way too many assumptions.

Lastly, Intel themselves claim they will have worse transistor density with Intel 3 than TSMC 3nm.
1713894604980.png
If it was just slightly worse, as you are suggesting, then they almost certainly would have done a " - ~" rather than a "-" since they also used "+~" elsewhere. I think that minus over there is doing a lot of heavy lifting. And tbh, I would not be surprised if this is specifically in reference to HP logic cells, and ignoring HD cells, SRAM density, analog, etc etc. I also think it's possible the signs for Intel 14A is a lot more wholistic though, since it also includes "mobile" in the target segment. We will see in a couple months ig.
 

Geddagod

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Intel 4 track 5.33,true?
HP
1713896792437.png
 

DavidC1

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If it was just slightly worse, as you are suggesting, then they almost certainly would have done a " - ~" rather than a "-" since they also used "+~" elsewherem
I don't think it's an ISO-process comparison but ISO-year comparison with Intel 3 being compared with N4 and 18A being compared to N3, etc, etc. The current rumor suggests 18A not being on par with N2 on density.
But ye I agree, I think intel is laser focused on perf/watt (prob perf/watt specifically for HPC too).
I don't mean performance per watt, but absolute performance leadership. Maybe they are even at the high end, but they are definitely behind at lower power.

Their traditional leadership on transistor performance was a full generation ahead, at a sacrifice of mobile-related specifics such as performance/watt and density.
 
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DavidC1

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Don Soltis (Senior principal engineer and chief architect for Xeon Efficient-core) said last year that Sierra Forest (Intel 3) has 100 billion transistors (approx).

Wild_C on twitter said last year that Sierra Forest (144) has a die area of 578 mm2 (approx).

With this we can directly calculate Sierra Forest on Intel 3 HD cell density at 173 MTr/mm2 (approx).
Except you are missing a big point.

Crestmont cores on Meteorlake are a mere 1mm2. So extrapolating that should mean 144mm2 for 144 cores, even if we take into account Intel 3 on SRF offering zero density gains. It doesn't have a lot of cache either. 108MB or something, which is relatively tiny.

If you take a Crestmont Cluster taking 6mm, then a 36 cluster Crestmont is ~220mm2. That's just the compute die we're talking about.

Either way you look at it, Sierra Forest is not very dense.
 
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Geddagod

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I don't think it's an ISO-process comparison but ISO-year comparison with Intel 3 being compared with N4 and 18A being compared to N3, etc, etc. The current rumor suggests 18A not being on par with N2 on density.
No I agree with you, but ISO-year would be comparing Intel 3 with TSMC 3nm. TSMC N3B has been out for a while.
18A is also likely to be compared with N3(E?P?) I think.
 

moinmoin

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I didn't notice it before but this slide is showing how IF continues to target HPC first, only adding mobile with 14A. Imo with the mobile market being such a crucial source for demand of high end chips IF won't be able to compete in leading edge high volume foundry market until it addresses that.
 

Doug S

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I didn't notice it before but this slide is showing how IF continues to target HPC first, only adding mobile with 14A. Imo with the mobile market being such a crucial source for demand of high end chips IF won't be able to compete in leading edge high volume foundry market until it addresses that.


Intel doesn't have the fab space to take on any high volume customers, so it doesn't matter. Until they are making wafers in Ohio they don't have to care about making mobile SoCs to drive volume, so it is probably no coincidence that doesn't come until 14A. Why set up your process to target customers you don't have the capacity for and therefore have no hope of getting?
 

DavidC1

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Intel doesn't have the fab space to take on any high volume customers, so it doesn't matter.
Not at all.

They need to get experience with actual customers. You don't get that experience without customers. You work on getting customers as you are working to optimize your process for that product line. One does not happen without the other.

Our learnings happen simultaneously at the brain and the body. Brain = your thought, and your theories, and body = actual doing.

They aren't optimizing it because they simply aren't ready. Looks like what someone said about Gelsinger at Intel is right. He talks in the if-the-glass-is-half-full perspective and rose-colored glasses all the time. Confidence is a positive but reality will take longer.

It makes more sense now why Qualcomm bailed on IF. Intel should have stuck with the IFS name. Because it is turning into an IF. IF they execute. IF they deliver. IF competitors stumble.
 
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Hitman928

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Here's a better link with a full press release. Looks like it might not be just N2+BSPD. I'll have to take more time to digest it.


TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap. A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks. Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15-20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

CoWoS®, SoIC, and System-on-Wafer (TSMC-SoW™ ): TSMC’s Chip on Wafer on Substrate (CoWoS®) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude. TSMC’s first SoW offering, a logic-only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

They also mention "NanoFlex" will be available starting with N2. Basically FinFlex continued on into the GAAFET tech.

Edit: They are comparing to N2P which should already have BSPD so it does look like a new node that comes with BSPD from the start. That will be a very quick iteration from N2 to N2P to A16 within 1 year (ish). Looks like they are trying to leave no doubt in who the fab leader is.
 
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Saylick

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Here's a better link with a full press release. Looks like it might not be just N2+BSPD. I'll have to take more time to digest it.






They also mention "NanoFlex" will be available starting with N2. Basically FinFlex continued on into the GAAFET tech.
Yeah, looks like TSMC A16 is the follow-up to N2P with better perf/W and density, essentially. Also, yay to marketing lingo for BSPD... First we had PowerVia and now we have Super Power Rail. lol
 

FlameTail

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Edit: They are comparing to N2P which should already have BSPD so it does look like a new node that comes with BSPD from the start. That will be a very quick iteration from N2 to N2P to A16 within 1 year (ish). Looks like they are trying to leave no doubt in who the fab leader is
TSMC Strikes Back!!

NODE WARS

10nm: The Cobalt Menace
N7 : The Rise of TSMC
N5 : The EUV awakens

Intel 4 : A New Hope
N3 : The Last FinFET
Intel 20A : The Revenge of Intel

N2 : Attack of the Nanosheets
Intel 18A : The Return of the King
A16 : TSMC Strikes Back
 
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Hitman928

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Anandtech has more info:


They are reporting that N2P is losing BSPD, so I'm back to thinking A16 is mainly N2P with BSPD (probably with some additional tweaks but nothing major). That leaves A14 as the next full node step after N2.

Additionally, it looks like TSMC has moved from a buried power rail implementation with BSPD to backside contacts (TSMC branded "Super Power Rail"). This is more advanced than Intel's Power Via approach. Looks like maybe they figured out how to make the backside contacts work and decided to make a new half node type step out of it rather than add a buried power rail version to the N2 family.

tsmc-bspdn.png
 

Saylick

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Anandtech has more info:


They are reporting that N2P is losing BSPD, so I'm back to thinking A16 is mainly N2P with BSPD (probably with some additional tweaks but nothing major). That leaves A14 as the next full node step after N2.

Additionally, it looks like TSMC has moved from a buried power rail implementation with BSPD to backside contacts (TSMC branded "Super Power Rail"). This is more advanced than Intel's Power Via approach. Looks like maybe they figured out how to make the backside contacts work and decided to make a new half node type step out of it rather than add a buried power rail version to the N2 family.

tsmc-bspdn.png
Wow, so TSMC delays their BSPD implementation on N2P so that they could go from Buried Power Rail to Backside Contacts. Considering that A16 is available in H2 2026, that’s not too far away. TSMC are probably aware that it adds significant cost and complexity, and customers are probably not entirely onboard with the added cost, so they probably made the decision to delay adding it until they absolutely need it for scaling reasons.

1714055118944.jpeg
TSMC is not the only fab pursuing backside power delivery, and accordingly, we're seeing multiple variations on the technique crop up at different fabs. The overall industry has three approaches for BSPDN: Imec's Buried Power Rail, Intel's PowerVia, and now TSMC's Super Power Rail.


The oldest technique, Imec's Buried Power Rail, essentially places power delivery network on the backside of the wafer and then connects power rail of logic cells to power contact using nano TSVs. This enables some area scaling and does not add too much complexity to production. The second implementation, Intel's PowerVia, connects power to the cell or transistor contact, which provides a better result, but at the cost of complexity.


Finally, we have TSMC's new Super Power Rail BSPDN technology, which connects a backside power network directly to each transistor's source and drain. According to TSMC, this is the most efficient technology in terms of area scaling, but the trade-off is that it's the most complex (and expensive) when it comes to production.


That TSMC has opted to go with the most complex version of BSPDN may be part of the reason that we've seen it removed from N2P, as implementing it will ultimately add to both time and costs. This leaves A16 as TSMC's premiere performance node for the 2026/2027 time-frame, while N2P can be positioned to offer a more balanced combination of performance and cost efficiency.