Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

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DisEnchantment

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Mar 3, 2017
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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

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N7 performance is more or less understood.
1587739093721.png

This year and next year TSMC is mainly increasing capacity to meet demands.

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.


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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.
 

FlameTail

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Dec 15, 2021
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SRAM scaling crashed with TSMC 3nm. N5 -> N3E, there is no imporvement in SRAM scaling.

But in N2, thanks to the adoption of new GAAFET transistors, SRAM scaling should pick up again?
 

SiliconFly

Golden Member
Mar 10, 2023
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Then what's this, "Now comes the interesting part, the upcoming N3E node is slightly more dense than the original N3."
Edit:

Anandtech article says "The trade-off is that N3E offers lower logic density than N3".

So, apparently Intel 3 is all set to take a clear lead over N3E this year.
 
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SiliconFly

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Mar 10, 2023
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These implications are enormous. This might directly put 20A roughly on par with N2 (cos N3->N2 isn't a big jump & intel 3->20A is expected to be similar). And when 18A comes out, it's gonna be clearly ahead of N2. Looks like process leadership after all.
 

SiliconFly

Golden Member
Mar 10, 2023
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N3E -> N2+BSPDN will be as big of a jump as N5 -> N3E

N5 -> N3E ; 30% density improvement.

N3 -> N2 ; >15% density improvement
N2 -> N2+BSPDN ; 10% density improvement

Source:
N2+BSPD, 18A-P & 14A are way off. Rest are pretty much inline with what I said. Meaning, process leadership late next year.
 
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randomhero

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Apr 28, 2020
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Depends what you call process leadership. Intel of yore had both superior process and huge volume. I will gladly say that Intel has leadership when they can match TSMC volume. Until then it's basically a power point victory.
Now, you have to start from somewhere...
 

Ghostsonplanets

Senior member
Mar 1, 2024
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Intel will do a presentation about Intel 3 at VLSI Symposium 24:

Advanced CMOS Technology
“An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and
SOC Product Applications” – Intel Corporation (Highlight Session – Paper T1.1) This paper presents Intel 3 FinFET technology fully optimized, providing 10% logic scaling,
performance and reliability improvement compared to Intel 4. Through transistor
enhancements, interconnect optimization, and design co-optimizations, up to 18% iso-power
performance gain is achieved over Intel 4. Intel 3 additionally enables a 210-nm high-density
standard cell, 1.2-V-native I/O transistors, deep N-well isolation, and long-channel analog
devices to provide full-featured technology design capabilities.

Screenshot_20240421_113253_Drive.jpg

Screenshot_20240421_113303_Drive.jpg
 
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Doug S

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Feb 8, 2020
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SRAM scaling crashed with TSMC 3nm. N5 -> N3E, there is no imporvement in SRAM scaling.

But in N2, thanks to the adoption of new GAAFET transistors, SRAM scaling should pick up again?

I think BSPDN is more important there because SRAM cells are more impacted by wiring congestion. To what extent it will benefit and whether that's a one time boost or will pay dividends in future shrinks I'm not really sure.
 

Ghostsonplanets

Senior member
Mar 1, 2024
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Honestly, it's fine, but Intel calling this Intel 3 is hella misleading. Also, SRAM shrink hopium is also dying. Maybe the perf/watt is good, idk.
View attachment 97506
This is a bit surprising tho. Wonder if Intel 20/18A's density jump over Intel 4/Intel 3 is really that bad.
Falls in line with the paper you shared some time ago that 18A MMP is basically the same as Intel 4.
 

FlameTail

Diamond Member
Dec 15, 2021
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Apple A16 Bionic = N4 = 113 mm² = 16 billion transistors
Density = 141.5 MTr

Apple A17 Pro = N3B = 103 mm² = 19 billion transistors
Density = 184.4 MTr
 

SiliconFly

Golden Member
Mar 10, 2023
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~150MTr is around N4. This isn't a misunderstanding, Intel quite literally called these their high density standard cells for Intel 3.
~150 MTr/mm2 is completely wrong (as discussed with witeken). Problem is he doesn't understand. His estimate is way off!

TSMC N3 HP density is 124 MTr/mm2. Intel 3 HP density is 135.74 MTr/mm2. Intel 3 HP density is higher than TSMC N3 by 10%.

And when it comes to HD, TSMC N3 is around 200 MTr/mm2.

So, basically what you are trying to say is:
When TSMC N3 HP is only 124, its HD is ~200.
And when Intel 3 HP is already 136, its HD is only a meager 150???

Your math is wrong.
 

Doug S

Platinum Member
Feb 8, 2020
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Got it. Looks like N3E has regression! Thats sad. They've given Intel 3 a free pass.

One thing we need to keep in mind (especially those who wrongly believe Apple will stick with N3B this fall) is that N3E brings FinFlex. Designers have to take advantage of it, but if properly applied we could easily see higher density with N3E than N3B. So I'm not sure I would look at N3B density and assume N3E is worse. TSMC's table shows that, but those numbers do not include the potential impact of FinFlex. It will be interesting to compare Apple's stuff this fall to last year's in that regard (I'm assuming they'll take advantage of FinFlex in A18/M4)
 

moinmoin

Diamond Member
Jun 1, 2017
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Wonder if Intel 20/18A's density jump over Intel 4/Intel 3 is really that bad.
As far as I understand the jump from Intel 4/3 to Intel 20/18A is less about any density increase and more about decreasing cost, increasing yield and significantly higher volume. Intel 4/3 are the last nodes in an unsustainable development of internal first/only nodes whereas Intel 20/18A are the first ones that should make IF actually competitive in the market.
 

SiliconFly

Golden Member
Mar 10, 2023
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One thing we need to keep in mind (especially those who wrongly believe Apple will stick with N3B this fall) is that N3E brings FinFlex. Designers have to take advantage of it, but if properly applied we could easily see higher density with N3E than N3B. So I'm not sure I would look at N3B density and assume N3E is worse. TSMC's table shows that, but those numbers do not include the potential impact of FinFlex. It will be interesting to compare Apple's stuff this fall to last year's in that regard (I'm assuming they'll take advantage of FinFlex in A18/M4)
Oh, those numbers do not?
Well, this is good news for TSMC N3E/N3P, and the next gen chips based on them.
Like shown in the video (and discussed in the other thread), I too remember reading that FinFlex is actually a part of N3B itself. So, N3E is definitely going to have some slight regression after all.