Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

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DisEnchantment

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Mar 3, 2017
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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

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N7 performance is more or less understood.
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This year and next year TSMC is mainly increasing capacity to meet demands.

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.


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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.
 

Tigerick

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Apr 1, 2022
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Don't see how.




Are they readying some other fab for sub-18A too?
According to Anandtech, Intel only entering 14A's risk production in late 2026. If everything goes smooth, then we should be expecting HVM by end of 2027.

 

Hans Gruber

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Dec 23, 2006
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It's easier to refer to 20A as true 5nm silicon. Intel made a big performance jump going from 14nm to 10nm with Alder Lake in performance. The efficient was much improved but still sucked compared to 7nm TSMC. Even worse when compared to 5nm TSMC silicon. I am crediting the silicon the 40 series Nvidia GPU's are on for crazy good efficiency. Just look at the power usage of a 4060 100-120w under full load.

Zen 5 will be on 4nm which is probably comparable to the 4N silicon Nvidia has been using on the 40 series cards. I think it's safe to assume AMD is losing 15% efficiency by not being on 3nm from launch on most of the Zen 5 CPU's. TSMC later iterations of 3nm will be much better than the N3 stuff that Apple is using.

I am expecting a huge jump in efficiency for Intel with Arrow Lake on 20A. The lack of hyperthreading is probably more related to Intel having much more real estate on the die going from 10nm to 5nm. They probably have more exotic options. AMD has lost their process advantage that they have had since moving to 7nm on Zen 2. If Zen 5 is as good as the leaks say it is. Then AMD should be in good shape on TSMC silicon.

The real interesting stuff will be the GPU wars. Intel, AMD and Nvidia are all on TSMC silicon. Not all silicon is created equal. It's not just the node but the process on a particular TSMC node that makes a difference in efficiency and performance.

TSMC makes great silicon. Their 3nm process price does not justify the cost based on performance. The energy efficiency is there but the cost for efficiency is not worth the price of admission. If anything, Intel will put direct pricing pressure on TSMC because of 18A and beyond.

If Arrow Lake (20A) is really strong when released. That will put pressure on AMD to switch over to 3nm for the entire Ryzen lineup sooner rather than later.
 

Hitman928

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Apr 15, 2012
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While the backside metal layers are indeed further from the active cooling interface, their thermal conductivity is far higher than the direct path. Even reducing copper to 300 W/mk would still put it at 200x that of the 1.5 W/mK the paper is using for the BEOL as per figure 14.

They are using copper for the backside metal. The 1.5 W/mK you are referring to is the effective thermal conductance of the front side BEOL layers, i.e., the effective thermal conductance of all the layers between the devices and the dielectric which connects the chip to the carrier silicon. The red on the bottom of the figure is the copper for the backside metal.

The primary constraint in using the backside metal layers for distributing heat over a larger area is the thermal conductivity from the transistors to those layers. I'm not sure how the buried power rails with occasional vias compares to Intel's PowerVia approach, but it's certainly plausible that PowerVia results in higher thermal conductivity to the backside metal.

They include a lot more vias in the first paper than they need to for the buried power rails to help with the thermals. That's part of the reason they reduced the thermal penalty from 2.2x to the 1.6x they quote. I wouldn't be surprised if even more vias with lower pitch needed for the PowerVia tech helps a bit more, but I have my doubts it is good enough to alleviate the problem.

They specify near the end of section II that an identical heat map is used for both the FSPDN and BSPDN models. That said, the 45% figure appears to be based on relative temperature increase? Which would only be valid if it's relative temperature compared to the active cooling interface, but that doesn't appear to be the case?

It's a 45% increase in absolute temperature in the hottest spot of the die with the FSPDN hottest spot being the baseline.

The delta C chart also in figure 18 implies that the actual thermal conductivity from heat source on the BSPDN model is closer to 1/3 that of the FSPDN model.

Anyway, I don't see any reason to doubt the silicon measurements which Intel has already shared. And I'll happily concede that bspd without appropriate mitigations is a 'heat sandwich'. Glad that Intel isn't relying on IMEC for process development inspiration.

This is showing the delta C between the hotspot and the surrounding silicon, not the overall temperature increase from ambient and yes, it shows that the thermal resistance in the BSPDN model around the devices is much higher due primarily to the thinned wafer. This is part of the reason I am skeptical of Intel's claims as you could easily cherry pick your test sample and what exactly you are measuring to make things look much better than they are. If you only use a CPU with low operating power as your test vehicle and are measuring absolute temperature in a way that is not near the actual devices, you could say that your BSPDN thermal results are in line with a FSPDN because the absolute temperature rise is not that much, even if the thermal resistance introduced with the BSPDN processing is in fact, much higher. On the other hand, if you did the same thing with a high power design and measured as close to the hotspots as possible, all of a sudden the much higher thermal resistance results in much higher absolute temperatures as well.

I'm not saying that is what Intel did in their test vehicle results, but the lack of almost any transparency into their test vehicle, how they measured, the scale on their graph, etc., makes me skeptical. I don't want to continue to belabor this issue either. Intel claims that they have a proprietary solution to completely mitigate the thermal issue with the BSPDN flow and if they really do, kudos to them, they'd have a real advantage here over everyone else. I just want to see a little more proof before being convinced. It wasn't long ago that Intel showed results with MTL having a large performance lead over Zen 4 at supposedly roughly the same power consumption, only to find out later that MTL was actually using like twice the power in their comparison. I know it's a completely different situation and group presenting, but I'd be skeptical of such results if anyone presented them with the lack of detail and transparency that Intel did when no one else seems to have a solution (yet).
 
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Saylick

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Sep 10, 2012
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I think the key things to note on this slide is the word “capacity” and how it’s not the same as “wafer starts”. It just represents Intels potential of fabbing these particular nodes, and it does not mean they will be actually cranking out these quantities. Imo, the capacities for the advanced nodes is still relatively low, so it make sense that they Product side is leveraging TSMC. But hey, let’s them claim 5N4Y I guess. Also interesting that the total capacity in thousand of wafers per month decreases a little bit in the short term.
 

dullard

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May 21, 2001
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I think it is one of the most important images to come out recently. Not only is it projecting plans further into the future than we've seen before (with dates for a node that wasn't publicly known before), but also shows that Intel 4/3 won't have much production capacity until late 2026. Heck, even Intel 20A/18A will soon have more capacity than Intel 4/3. So that helps explain Intel's use of TSMC and continued use of Intel 7 resulting in an array of niche products. Finally it shows one more reason to think of 4 -> 3 as a half node and 20A -> 18A as a half node.

But when I posted about this image in another thread, all people wanted to talk about was Intel 7 can be pushed to high power levels.
 

dullard

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May 21, 2001
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20A (2024) -> 14A (2026) -> 10A (2027)?

What I am trying to get my head around is that Intel CEO said this also:

Which part of that article conflicts in your head? This part?
Gelsinger has emphatically said Moore's Law is "alive and well." In fact, he even said Intel could surpass the pace of Moore's Law at least until 2031 and has promoted "Super Moore's Law," a strategy to boost transistor count using 2.5D and 3D chip packaging technologies such as Foveros.

The reality as described in the article is subtle. We can toss in a lot of transistors to keep up with (or exceed) Moore's law for a while, but it is just becoming too financially burdensome to try to keep up for long.
 

Doug S

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@beginner99 noted this on RWT - an Apple patent for using BSPDN to split the SRAM control lines, half on the front side and half on the backside. That should remove one of the bigger roadblocks that had stalled density improvements in cache, as well as reduce latency. While BSPDN will increase cost it will provide some interesting options for those willing to pay it.

https://patents.google.com/patent/US20230299068A1
 

FlameTail

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Dec 15, 2021
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@beginner99 noted this on RWT - an Apple patent for using BSPDN to split the SRAM control lines, half on the front side and half on the backside. That should remove one of the bigger roadblocks that had stalled density improvements in cache, as well as reduce latency. While BSPDN will increase cost it will provide some interesting options for those willing to pay it.

https://patents.google.com/patent/US20230299068A1

Interesting. So since this is an Apple patent, will they license it to foundries?
 

ashFTW

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Sep 21, 2020
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Interesting. So since this is an Apple patent, will they license it to foundries?
As I understand things, a process doesn’t necessarily dictate how SRAM or any other circuit is designed. So Apple can use it with TSMC, or any another fab, exclusively in their own SRAM designs. But note that the patent seems to be FinFET only, so it would not apply to N2, where BSPDN is first introduced by TSMC. N2 is GAA. @Doug S Is there a GAA version of this patent?
 

NostaSeronx

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Sep 18, 2011
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January 2024: Canon is expected to ship NZ2C machines this year. For 1/10th the cost of EUV:
Low-NA: $1xx million tool => NIL: $1x.x million tool

Speed, price, quality => clearly chose price and quality.

Other target cost stuff:
M1~M3 at 56-nm on ArFi SADP = M1~M10 at 56-nm on NIL
 
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Doug S

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Is there a GAA version of this patent?

The transistor technology is irrelevant. SRAM has the same basic layout with bitlines and wordlines whether it is implemented with 6T or 8T or whatever, and whether those transistors are planar, FinFET, GAA or CFET. The patent describes how SRAM control lines are handled differently with BSPDN, that's the "invention" of the patent.

One can assume that TSMC has been experimenting with BSPDN for some time independently of GAA, just as Intel did, and as Apple is their biggest partner in that research probably designed something approximating what is described in the patent using current gen transistors. I haven't read the patent in detail (and as I'm not a process engineer some of it will be Greek to me) but typically patents for all technology will include some sort of disclaimer about where it can be used. In this case mentioning the transistor technology, and asserting the patent's validity with future transistor types (GAA would probably though not with certainty be called out)
 
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dullard

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I don’t think anyone was stating otherwise, including Intel.

If folks got the messaging mixed up, that is on them.
I'm pretty sure Ian is taking a direct jab at this article at Tom's Hardware when he says "or you have a title suggesting it":
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There was an edit to the article that clarifies that this is 10A development only in 2027. But they left the clearly misleading subtitle. And I personally take offense that the subtitle equates 10A to 1 nm. 10A is meant to look like 10 Å (Angstroms), but nothing about 10A is actually 1 nm.
 
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