Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

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DisEnchantment

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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

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N7 performance is more or less understood.
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This year and next year TSMC is mainly increasing capacity to meet demands.

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.


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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.
 

Saylick

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So do you think there will always be processes with and without BSPD moving forward?
I think this is a logical conclusion. BSPD adds cost but provides performance and density improvements. For those who are more sensitive to cost than performance and/or density, they probably prefer a more "conventional" node.
 

ashFTW

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I think this is a logical conclusion. BSPD adds cost but provides performance and density improvements. For those who are more sensitive to cost than performance and/or density, they probably prefer a more "conventional" node.
There is also a huge cost - that has to be ultimately passed on to the customer - associated with developing and maintaining two process variations. I think that once BSPD and all that it entails is well understood, it will become the norm.
 

moinmoin

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In an ideal world, all leading foundries like TSMC, Samsung, Intel, GF, each should have 25% share of the market, should collaborate with each other on leading edge technologies, and each should have some special offerings to differentiate one from other. But thats just dreaming.
In a way this is already happening, there's historically co-ownership in critical companies like ASML, and as @Thibsie mentioned there's fundamental research done by universities and inter-university organizations like indeed IMEC.

The question was essentially regarding the nature of the differentiation of the foundries. Intel had a huge advantage for a very long time. TSMC had a significant advantage in handling EUV for quite some time. This points to the in-house knowledge (beyond what public research and shared companies offer) being a significant aspect of the final product.
 

moinmoin

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It's Intel manufacturing in its existing foundries. I don't know how similar UMC's setup is to Intel's, but I would think aside big blocks like ASML machines they are actually very proprietary and not easily exchangeable. So I'd think it's Intel's node (14nm specifically) at the very least as a base. Then the question is whether it's faster and less costly to adapt Intel's node to UMC's tools or UMC's tools to Intel's node. While I expect both to happen to a degree, I'd think adapting UMC's tools would be faster and less costly, especially since UMC unlike Intel has a track record of supporting its customers with standardized tools and solutions. And that's also what IFS can and must learn from.
To follow up on this topic, this is what Pat told Ian:

"I don't think we would have learned nearly as much as we’re going to do with this partnership with UMC.

They know how to create and support these customers - they have a rich set of customers that want to move on to this node. [Those customers] have been working the 16nm and their 22nm, and they want to move onto this node. But [UMC] also know how to do many PDKs [rather than just one] - the PDK for high voltage, for RF, for analog purposes, for power delivery purposes and so on. They’ve perfected how to get the portfolio of 12 done, and Intel doesn't do that.

We essentially did one process node for essentially one class of design - being high performance leadership compute. UMC has mastered how to make multiple nodes off of one core investment. So we believe this is a great investment for them, because they're going to be expanding their supply base, using a factory that I’m going to have.

[The fab,] while capitalised, will bring some level of new equipment in to deliver that 12nm, but mostly it’s in a factory that I’ve already built and have running. They're going to be able to go to their customers and say they have a more resilient supply chain, they have a US supply chain, alongside their Asian supply chain. So it’s good for their customers, and they already have customers that are anxious for this node. We’ve had a great response from some of their customers, saying they’re ready to move major design volume to this as well. I think we’re going to be able to take this factory, learn a lot through the process as well. What if I put my best people working on a 12nm node?

I think UMC has talent and expertise here that’s just going to complement the Intel factories. I’m really quite excited about the partnership, super excited that Jason Wang (UMC Co-President) is here [at the event], and I think It’s going to be a winner for both of us.
"


There is a big difference between being able to do something slowly in a lab with low yields versus high volume, low defect production.
You can do something slowly and still have a high yield.
 

SiliconFly

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So do you think there will always be processes with and without BSPD moving forward?
CPUs with performance cores that have higher boost clocks will definitely benefit a lot from bspd. Not so much with efficiency/dense cores, caches and other logic like i/o, etc. Not sure about GPUs though, but I think they'll prefer bspd too.
 

DavidC1

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CPUs with performance cores that have higher boost clocks will definitely benefit a lot from bspd. Not so much with efficiency/dense cores, caches and other logic like i/o, etc. Not sure about GPUs though, but I think they'll prefer bspd too.
Backside boost benefits everything because of the potential ease of routing not having to have power done all through one side, so it also comes with density benefits.

Low cost designs may not want it but all others potentially can.
 
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Khato

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are you daft?
You're bonding a thinned wafer on top of logic there, it's like the opposite.
You make a heat sandwich.
With bspd the functional metal layers are now between the transistors and the carrier silicon, whereas before the transistors were on the carrier silicon. I highly doubt that those layers make a notable difference in the thermal resistance between transistors and heat sink. What minor difference is present will be easily negated by the lower resistance afforded by bspd.
 

Hitman928

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With bspd the functional metal layers are now between the transistors and the carrier silicon, whereas before the transistors were on the carrier silicon. I highly doubt that those layers make a notable difference in the thermal resistance between transistors and heat sink. What minor difference is present will be easily negated by the lower resistance afforded by bspd.

What do you mean by functional metal layers? Do you mean the signal traces? The signal traces being between the transistors and the carrier silicon isn't the problem, it's the highly thinned wafer which greatly reduces the ability of the heat to spread laterally before exiting the die which dramatically increases the hotspot effect. You also have a dielectric layer between the carrier wafer and the logic wafer which adds additional thermal interfaces and acts as a bit of an insulator though this is a smaller effect than the thinned wafer.

Having wide (relative) metals from the backside power network (including the TSVs) can help alleviate the issue with the thinned wafer and you can add some thermal metalization as well to help but it doesn't fix the problem. How much you can alleviate the issue depends on how exactly the wafer is processed (e.g., how thin it is, how the TSVs are implement), how wide the TSVs are, and the construction of your BSPDN. One paper I saw got the thermal increase (K/mW) down to about a 1.5x - 1.6x penalty with the BSPDN over the traditional wafer. Without the metalization, it was a 2.2x increase. That was with a wafer thinned to 500 nm. If thinned further, it got even worse. This will be a major problem for high performance CPUs which already hit thermal limits on the regular.
 

Khato

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The 1.5x-1.6x and 2.2x increases being referred to indicate that this would be the referenced paper? https://ieeexplore.ieee.org/document/9899603 If so, I don't see any description of using a different model for a fspd reference? Instead it sounds like they're just varying the thickness of the thinned Si substrate in the bspd model, with 1.0x being a 1mm substrate?

Another interesting one to look at is https://ieeexplore.ieee.org/document/10183952 The modeling approach of placing equivalent heat sinks on both the front and back side isn't realistic of course, but in some respects it provides more data on the comparison. The heat flux distribution between front and back side on the traditional fspd was of particular interest I thought. It does make sense that more heat could travel through the back side given both the difference in thickness and that bulk copper thermal conductivity is almost 3x that of silicon.

Anyway, no disagreement that hot spotting is an issue for consideration in both front and back side power delivery. I'm just not certain that bspd is markedly worse than fspd in that regard. Unless, of course, it's intentionally designed to be far worse.
 
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Hitman928

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The 1.5x-1.6x and 2.2x increases being referred to indicate that this would be the referenced paper? https://ieeexplore.ieee.org/document/9899603 If so, I don't see any description of using a different model for a fspd reference? Instead it sounds like they're just varying the thickness of the thinned Si substrate in the bspd model, with 1.0x being a 1mm substrate?

Another interesting one to look at is https://ieeexplore.ieee.org/document/10183952 The modeling approach of placing equivalent heat sinks on both the front and back side isn't realistic of course, but in some respects it provides more data on the comparison. The heat flux distribution between front and back side on the traditional fspd was of particular interest I thought. It does make sense that more heat could travel through the back side given both the difference in thickness and that bulk copper thermal conductivity is almost 3x that of silicon.

Anyway, no disagreement that hot spotting is an issue for consideration in both front and back side power delivery. I'm just not certain that bspd is markedly worse than fspd in that regard. Unless, of course, it's intentionally designed to be far worse.

Yes, the first one is the paper I was referring to. The baseline comparison is to a traditional front side network. See the first paragraph of section IV:

This results in an overall temperature increase of 60% for the BS-PDN case compared to the conventional FS-PDN configuration.

This was their best result with the wafer thinned to 500 nm and lots of wide metals added to the backside (it also is the same if the wafer is left a bit thicker at 2.5 um but no metals added). The thing that the paper doesn't account for is that the BSPDN will allow for a more efficient power transfer to the FETs which will allow it to reduce power consumption but the numbers I've seen don't show near enough of a power reduction to negate the thermal issue. The paper's results are entirely based on thermal simulations so maybe real world results aren't quite as bad, but unless they royally screwed something up, it shouldn't be too far off of actual measurements.

The second paper using heatsinks on the front side and backside makes their results meaningless. The heat flux through the front side versus backside is exactly as I would expect given the double heatsink setup because it completely changes how heat flows through the chip and has no real world implications (in a real packaged design, the heat flow is even more one sided and drastically so). The more interesting part of the paper is the effect that different backside metal materials has on the temperature, though again, I don't know how much this is really true given an actual package design with the heatsink on only one side.

BSPD isn't intentionally designed to be much worse thermally, it's just a natural consequence of the design. Just like using larger FETs doesn't intentionally increase the gate capacitance, it's just a natural consequence of the design. Even Intel says that BSPDN causes thermal issues, but they do claim that they've included mitigation techniques in their BSPDN process / 4nm test vehicle that brings the thermals in line with a FSPDN 4nm design. They haven't revealed what those techniques are and the plot they showed is a little, uhh, fuzzy, in this regard, so they might be stretching the truth there a bit, but they at least are projecting confidence that they've solved this problem with BSPDNs. We'll hopefully see fairly soon how true this is and maybe they'll even reveal more details of their process (wafer thickness, metal used, etc.) as we get closer.
 
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Khato

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Yes, the first one is the paper I was referring to. The baseline comparison is to a traditional front side network. See the first paragraph of section IV:
Again, since they didn't specify a different model used for fspd and the only reference to FS-PDN in the data is an arrow pointing to a spot on the curves at 200um Si thickness I'm inclined to believe that they're normalizing to the same model at the 1mm bulk silicon thickness. This probably isn't too different from a fspd model.
This was their best result with the wafer thinned to 500 nm and lots of wide metals added to the backside (it also is the same if the wafer is left a bit thicker at 2.5 um but no metals added).
I wouldn't call a single250nmx210nm backside metal layer at a 500nm pitch to be lots of wide metals. Unfortunately I haven't seen numerical figures on Intel's implementation, but the cross section pictures they've released look to have the backside M0 at comparable thickness to the thinned Si, and they only get larger from there. Their results/conclusions are 100% correct for their model, but how closely does that model relate to actual bspd processes?

The second paper using heatsinks on the front side and backside makes their results meaningless. The heat flux through the front side versus backside is exactly as I would expect given the double heatsink setup because it completely changes how heat flows through the chip and has no real world implications (in a real packaged design, the heat flow is even more one sided and drastically so). The more interesting part of the paper is the effect that different backside metal materials has on the temperature, though again, I don't know how much this is really true given an actual package design with the heatsink on only one side.
It's no more meaningless than a theoretical bspd model. It's providing different data that can be made use of for implementation considerations.
 

Hitman928

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Again, since they didn't specify a different model used for fspd and the only reference to FS-PDN in the data is an arrow pointing to a spot on the curves at 200um Si thickness I'm inclined to believe that they're normalizing to the same model at the 1mm bulk silicon thickness. This probably isn't too different from a fspd model.

I'm not sure what to say as they clearly did specify different cross-sections and heat modeling for FS and BS PDNs. See figures 1 and 4. Additionally, they give commentary multiple times that their baseline comparison is to a standard FS-PDN.

This paper presents a modeling analysis of the thermal impact of the introduction of the backside power delivery network
In Section IV, the modeling results for the thermal comparison between the conventional FS-PDN and the BS-PDN configuration and the parameter sensitivity are discussed.
In order to assess the thermal performance comparison of the conventional frontside and the backside power delivery configurations, both the local heat spreading impact as well as the package level thermal behavior should be considered.

You can also look at figure 12 where they show how they are normalizing the temperature increase of the BS-PDN to a FS-PDN with 200 um thick substrate. I honestly don't know how much clearer they could make it.






I wouldn't call a single250nmx210nm backside metal layer at a 500nm pitch to be lots of wide metals.

They give results on multiple metal thicknesses, TSV arrays, and pitches. So I'm not sure what you mean.

Unfortunately I haven't seen numerical figures on Intel's implementation, but the cross section pictures they've released look to have the backside M0 at comparable thickness to the thinned Si, and they only get larger from there.

Intel hasn't released any detailed info as far as I'm aware but their cross sections are absolutely not to scale. If I had to guess, Intel is probably keeping the wafer a little thicker (this will degrade electrical performance compared to thinner wafer but provide better thermal performance), using a lot of electrically unnecessary metalization for thermal performance, and maybe using different types of metal on the back-end to help mitigate the thermal issues. Maybe they also have some secret sauce that they've developed that they aren't willing to share, I doubt it, but it's possible. Ultimately I think they'll do a good job alleviating a lot of the thermal problem, but it will still be there and will be a problem for designs that would already be hitting thermal limits with a FS-PDN. I could very well be wrong here, time will tell. If they have figured out how to mitigate the thermal issue, hopefully they share at least some of the details so others can build on their research.

Their results/conclusions are 100% correct for their model, but how closely does that model relate to actual bspd processes?


It's no more meaningless than a theoretical bspd model. It's providing different data that can be made use of for implementation considerations.

The paper I linked is much more realistic than the second paper you linked to. They actual include the packaging and proper heat flux through the die and are giving you multiple values of wafer thickness, metal thickness, TSV processing, and TSV size and pitch. Your link has almost no relevance because they don't include the packaging, give limited substrate thickness results (and don't go as thin as the first paper which is required for actual BS-PDN flows that I've seen), and add a heatsink directly to both side of the die. This completely changes the heatspot effect and how heat is able to be moved away from the devices to ambient. It's kind of like testing a high power GPU with a 3 fan heatsink in an air conditioned room without a case and concluding that it has no cooling problems so it should be fine inside of a car, right next to the engine. It's so far away from the real life situation that it's going to be put in, that the results don't mean anything. Like I said, the only thing I think you can draw from the second paper is that different metal composites are better at being used as thermal vias than others but to what degree this will hold in an actual packaged die is unknown because they didn't simulate it that way.
 
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Hitman928

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If you don't believe me that BSPDN introduces thermal issues, maybe listen to IMEC?

Extreme wafer thinning to a few 100nm of Si is required to expose the nTSVs and minimize their resistivity (and hence, IR drop). This severely restricts the allowed thickness variation, which may be induced during the different wafer thinning steps. Imec collaborates with several partners to improve the chemistries used for etching. The final wet etch, for example, enables a highly selective soft-landing process stopping on the SiGe layer. In the final step of the thinning process, the SiGe etch stop layer is removed in a dedicated chemistry where very high selectivity to Si is required. This way, the Si capping layer can be exposed with a total thickness variation below 40nm.

Another concern is the thermal impact on the device self-heating due to the extreme thinning of the (otherwise heat-dissipating) Si substrate. Preliminary modeling work indicates that the self-heating effect can, to a large extent, be countered by the metal lines in the wafer’s backside, which provide additional lateral thermal spreading. More detailed thermal simulations are currently ongoing to gain more insights. [6]

The reference they use at the end of the quote [6], links to the exact paper I linked to earlier. As the paper showed, you can mitigate the thermal issue (they were able to cut the thermal penalty in half) with a smart metalization scheme, but the increase was still significant even after the metal was added. I'm sure additional research in this area is being done, including obviously by Intel, to reduce this even more, but I have my doubts that they'll completely neutralize the issue. For lower power designs, I'm quite sure it will be good enough. For high power/high frequency targets, that's where I have my doubts.
 
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Khato

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I'm not sure what to say as they clearly did specify different cross-sections and heat modeling for FS and BS PDNs. See figures 1 and 4. Additionally, they give commentary multiple times that their baseline comparison is to a standard FS-PDN.
Figures 1 and 4 are referred to in their Introduction and BS-PDN Thermal Considerations sections, not their Thermal Modeling Test Case section. They only specify a BS-PDN thermal model - where's the specifications of the FS-PDN model? It's entirely plausible that they did also run a FS-PDN model, but I don't see any references to it in their paper.
You can also look at figure 12 where they show how they are normalizing the temperature increase of the BS-PDN to a FS-PDN with 200 um thick substrate. I honestly don't know how much clearer they could make it.
Which is exactly what I referred to. A single arrow pointing to a spot on the curves at 200um Si thickness. Reading through the entire paper my take is that they're assuming that FS-PDN is equivalent to their BS-PDN model with a 200um Si substrate.
They give results on multiple metal thicknesses, TSV arrays, and pitches. So I'm not sure what you mean.
You said their 'best result' was a 60% increase with 'lots of wide metals added to the backside'. The 60% result was with the 210nm backside M0 thickness. It reduces to 50% at the 700nm backside M0 thickness. Can reduce far more with an actual bspd implementation that includes more than a single metal layer. They really should have at least simulated with 2 back side metal layers to allow for them to conduct heat in 2 dimensions.

If you want one that's attempting to more accurately model an actual chip this one is decent - https://ieeexplore.ieee.org/document/10019349

Anyway, I'd say that my point is that each of these research papers proves their specific premise. Which is quite important to keep in mind - they're not proposing ideas on how to improve bspd thermal characteristics, they're just modeling certain aspects. Intel's data by comparison is from actual silicon which includes mitigation techniques. Not to mention the PowerVia approach to bspd compared to the buried power rail variant that the papers tend to use.
 

Hitman928

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Figures 1 and 4 are referred to in their Introduction and BS-PDN Thermal Considerations sections, not their Thermal Modeling Test Case section. They only specify a BS-PDN thermal model - where's the specifications of the FS-PDN model? It's entirely plausible that they did also run a FS-PDN model, but I don't see any references to it in their paper.

Which is exactly what I referred to. A single arrow pointing to a spot on the curves at 200um Si thickness. Reading through the entire paper my take is that they're assuming that FS-PDN is equivalent to their BS-PDN model with a 200um Si substrate.

You said their 'best result' was a 60% increase with 'lots of wide metals added to the backside'. The 60% result was with the 210nm backside M0 thickness. It reduces to 50% at the 700nm backside M0 thickness. Can reduce far more with an actual bspd implementation that includes more than a single metal layer. They really should have at least simulated with 2 back side metal layers to allow for them to conduct heat in 2 dimensions.

If you want one that's attempting to more accurately model an actual chip this one is decent - https://ieeexplore.ieee.org/document/10019349

Anyway, I'd say that my point is that each of these research papers proves their specific premise. Which is quite important to keep in mind - they're not proposing ideas on how to improve bspd thermal characteristics, they're just modeling certain aspects. Intel's data by comparison is from actual silicon which includes mitigation techniques. Not to mention the PowerVia approach to bspd compared to the buried power rail variant that the papers tend to use.

You're right, they did show that increasing the backside metal thickness significantly (3.33x) does get you a little better thermals (8.3% reduction) than what I quoted. You are purely speculating though that more backside metal layers will result in far more thermal reductions. I don't believe this is true at all. The reason is because there is no thermal path in that direction for cooling (it technically does exist but it's very high thermal resistance). Almost all of the heat flows through the top of the chip to the cooling elements (i.e., heatsink). The reason the wide (and yes, it is very wide, relatively speaking) backside metals help is because it allows the heat to travel laterally before going vertical to reach the cooling elements. Adding additional metals deeper into the chip should only have a minimal effect on thermals. You already see a very small effect from a very large increase in the metal thickness, once you have to go through vias and additional layers, there won't be much of any benefit to speak of. The goal is to spread the heat laterally away from the active devices, not in the opposite vertical direction from the active cooling.

I do appreciate the paper you linked. It has some good data. It is also from the same IMEC group of the paper I posted and even has a couple of the same authors. It seems like they took their research from the first paper where they used generic hotspots and expanded it to an actual CPU. In the end, their findings were very similar, even with a full BS-PDN as you would put it.

The thermal performance of 2D IC with BSPDN is ~45% worse (in the hotspot zone) than the FSPDN counterpart due to the thinning of silicon substrate and the flipping and bonding steps required for BSPDN process.

I'm not sure as it is not clear to me, but it seems they are getting a reduced thermal penalty compared to their earlier paper because they are comparing at iso frequency versus iso power of the previous paper. So the additional efficiency produced by the BSPDN allows for reduced power which obviously helps the thermal situation. Either way, this paper only reaffirms that using a BSPDN causes thermal problems. They can be mitigated to a degree, but so far, no one that I am aware of has shown research where they can reduce it to the point where it is not a significant factor. Like I said earlier, maybe Intel has it figured out to be a complete non-issue, but I am skeptical of that claim until real proof is shown because everyone else that has researched it or commented on it agrees that it is an issue.
 
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Khato

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You're right, they did show that increasing the backside metal thickness significantly (3.33x) does get you a little better thermals (8.3% reduction) than what I quoted. You are purely speculating though that more backside metal layers will result in far more thermal reductions. I don't believe this is true at all. The reason is because there is no thermal path in that direction for cooling (it technically does exist but it's very high thermal resistance). Almost all of the heat flows through the top of the chip to the cooling elements (i.e., heatsink). The reason the wide (and yes, it is very wide, relatively speaking) backside metals help is because it allows the heat to travel laterally before going vertical to reach the cooling elements. Adding additional metals deeper into the chip should only have a minimal effect on thermals. You already see a very small effect from a very large increase in the metal thickness, once you have to go through vias and additional layers, there won't be much of any benefit to speak of. The goal is to spread the heat laterally away from the active devices, not in the opposite vertical direction from the active cooling.
While the backside metal layers are indeed further from the active cooling interface, their thermal conductivity is far higher than the direct path. Even reducing copper to 300 W/mk would still put it at 200x that of the 1.5 W/mK the paper is using for the BEOL as per figure 14. The primary constraint in using the backside metal layers for distributing heat over a larger area is the thermal conductivity from the transistors to those layers. I'm not sure how the buried power rails with occasional vias compares to Intel's PowerVia approach, but it's certainly plausible that PowerVia results in higher thermal conductivity to the backside metal. Which both reduces hot spotting and allows the heat more area to traverse through the poorly conducting BEOL. This is demonstrated nicely in figure 16.

I'm not sure as it is not clear to me, but it seems they are getting a reduced thermal penalty compared to their earlier paper because they are comparing at iso frequency versus iso power of the previous paper. So the additional efficiency produced by the BSPDN allows for reduced power which obviously helps the thermal situation. Either way, this paper only reaffirms that using a BSPDN causes thermal problems. They can be mitigated to a degree, but so far, no one that I am aware of has shown research where they can reduce it to the point where it is not a significant factor. Like I said earlier, maybe Intel has it figured out to be a complete non-issue, but I am skeptical of that claim until real proof is shown because everyone else that has researched it or commented on it agrees that it is an issue.
They specify near the end of section II that an identical heat map is used for both the FSPDN and BSPDN models. That said, the 45% figure appears to be based on relative temperature increase? Which would only be valid if it's relative temperature compared to the active cooling interface, but that doesn't appear to be the case? The delta C chart also in figure 18 implies that the actual thermal conductivity from heat source on the BSPDN model is closer to 1/3 that of the FSPDN model.

Anyway, I don't see any reason to doubt the silicon measurements which Intel has already shared. And I'll happily concede that bspd without appropriate mitigations is a 'heat sandwich'. Glad that Intel isn't relying on IMEC for process development inspiration.
 

FlameTail

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