Originally posted by: Nemesis 1
I know that last bit and the following is not about Larrabee . But you said we have no metrics . I think we do .
*snip*
This paper will provide a brief background on ISA, and then give an overview of the new instructions and capabilities of the Intel AVX and advantages of these innovative instructions across various applications and programming models.
I mean experimental data, not speculation on the lower/upper limits we can expect the end product to fall between.
I have no issue with making attempts to
bound the expected power-consumption of Larrabee, provided this too is done with a rational methodology (which you are doing).
But do not conflate our speculative bounding of the power-consumption question (albeit as justified and rational as one can be about it) with that of actually having data regarding the power profile of the actual Larrabee architecture as implemented in silicon.
There is no way to estimate Larrabee's power consumption without knowing operating voltage and clock frequency at a minimum, and even then we'd still be making liberal guesses regarding xtor density and types (but we could make justified bounds on these based on Atom performance and die-size as you point out).
Intel people are not dumb, as you know, and I think we both can agree we'd be fooling ourselves to think Intel isn't watching themselves like a hawk regarding everything they put into the public domain when it comes to Larrabee's performance and power-consumption as they KNOW this is a big question of interest to their competition.
No way we'll be able to piece this one together by stringing together the right IDF presentations and press releases, its all been scrutinized already before it went public.