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L2 cache on CPU?

life24

life24

Senior member
Hello,
Could you give me more explain about it? I'm beginner in these concepts.

The L2 cache is on the same processor chip and uses the same die as the CPU, however, it is still not part of the core of the CPU.
 
Try a search engine like Google or Bing. You may find better answers to simple questions that way than by asking here:

https://www.techopedia.com/definition/8049/level-2-cache-l2-cache

In summary, it's a bit like RAM except that it's a lot faster. CPUs go to a lot of trouble making sure that frequently-accessed data resides somewhere in cache so that they don't have to use system memory. System memory is slow enough that it can make a CPU lag just from having to wait around for the memory controller to respond to requests for data from memory.
 
Pretty much with no cpu you are going to run it maximum potential for even if a CPU has X calculation units at Y ghz you have to feed the cpu useful information so it can calculate useful data.

Thus the cpu has a series of input funnels, things like L2 Cache, L3 Cache, sometimes L4 cache, then ram, then hard drive and the goal is to get these various caches and rams to have the lowest amount of latency possible. Latency is the amount of time to retrieve 1 instruction / 1 piece of data. Bandwidth is the amount of instructions or data it can retrieve all at once. Memory size is the amount of instructions or data you can keep in that level of cache, ram, or hard drive.

Pretty much the faster you can get the data to the cpu the faster real world performance your cpu can do for it can take advantage of all that horsepower your cpu has. Thus it is a big deal on the latency of your l2 cache and so on.

There is another big deal on something called prefetch where the cpu is making intuitive leaps where if I am computing this math problem I probably should retrieve the next predicted amount of data and move it to the closest cache possible to make it faster to retrieve. Think of it like I am mixing the dry ingredients for a baking, then I need to gather up the liquid ingredients next, followed by the mixing equipment. I do not need to get out the baking pan yet, but lets prewarm the oven for while I am not at the pan state it takes X minutes to warm up the oven and so on. It is planning out the sequence of events to reduce latency as much as possible.

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Larger L2 and L3 caches help up to a point but after a certain amount you get diminishing returns.

Higher amount of bandwidth have very little improvements in cpu tasks, but in gpu tasks higher amount of bandwidth makes huges differences in gpu workloads.

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Many of the cpu improvements of the last few years have been realized by figuring out ways to fetch instructions faster with smarter prefetch engines, lower latency cache, etc.
 
l2 on the mobo was the de facto standard before PPro/PII. Some old systems simply had no l2 at all, and when they did add l2, it was always on the motherboard. I know 486s had that, not sure if 386s had l2.
 
DrMrLordX said:
l2 on the mobo was the de facto standard before PPro/PII. Some old systems simply had no l2 at all, and when they did add l2, it was always on the motherboard. I know 486s had that, not sure if 386s had l2.
Click to expand...

Remember the K6-3? It used the on-board L2 cache as an effective L3 cache, due to it having on-die L2 cache.

With 256KB L2 and 512/1024KB L3 it was quite a beastly CPU back in the day.
 
Celerons, the original cache less process 😛

So the first Celerons was 1998, they are now so old that they just turned 18, they are no longer jailbait with their cache less nature.
 
life24 said:
Hello,
Could you give me more explain about it? I'm beginner in these concepts.

The L2 cache is on the same processor chip and uses the same die as the CPU, however, it is still not part of the core of the CPU.
Click to expand...

These days, a typical design will have the L2 shared between 2 or more CPU cores. Each core has their own L1 caches and a bus out to a shared L2. Physically, everything is smushed together on the die but conceptually since the L2 works with 2 or more cores it isn't counted as totally part of either.
 
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