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L1, L2, L3 cache

The cache is basicly ram for the CPU. The L1 cache is where the information is stored just prior to being executed by the CPU, the L2 cache feeds the L1 cache. IE if there is some data that is needed, and it's not in the L1 cache, it looks to the L2 cache. If a cpu has an L3 cache, then it stores data as well, and will be looked at next if the L2 cache doesn't have what it's looking for. Then it will look to the ram. Each lvl of cache is slightly slower than the next, but still much faster than ram.
 
Originally posted by: roguerower
What does it do exactly. i.e. if i'm getting a Pentium M with 2mb L2 that equals what?
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it = mega low latency memory super close to the core ... 😉 .. which is a good thing,

if i had it my way i would glue a ddr stick to my Athlon 64 and pass it off as a hybrid on ebay for mega $$'s 😛
 
Originally posted by: RichUK
Originally posted by: roguerower
What does it do exactly. i.e. if i'm getting a Pentium M with 2mb L2 that equals what?
Click to expand...

if i had it my way i would glue a ddr stick to my Athlon 64 and pass it off as a hybrid on ebay for mega $$'s 😛
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The funny thing is, that someone would see it and believe that you had made something new and jack up the price til u were a millionaire.
 
Originally posted by: stevty2889
The cache is basicly ram for the CPU. The L1 cache is where the information is stored just prior to being executed by the CPU, the L2 cache feeds the L1 cache. IE if there is some data that is needed, and it's not in the L1 cache, it looks to the L2 cache. If a cpu has an L3 cache, then it stores data as well, and will be looked at next if the L2 cache doesn't have what it's looking for. Then it will look to the ram. Each lvl of cache is slightly slower than the next, but still much faster than ram.
Click to expand...

actually L3 cache like the one used on the Intel EE's, were just normal SD RAM, and did not run at te same clock rate as the L1, and L2 cache's, and therefore was pointless marketing, becasue the L3 cache was not quicker than the normal RAM being used.

O well who cares intel sucks 😛

 
Originally posted by: Cheesetogo
What is the point of a level 3 cache?
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its because Intel quickly wanted to add more numbers (I.E. 2Mb Cache), to justify the extreme'ness of their 3.43 extreme edition over the 3.6 P4 out at the time. (Also they added the 1066 FSB all numbers again) pretty sad if you ask me. (because it was no quicker then the normal P4's, sometimes it was a tad but not enough to warrant 3 times the price).

Also they didn?t have the time to be able to re-engineer there chips or fab?s to accommodate 2Mb of L2 cache on the CPU die within a time scale they would have liked (competing with AMD's release), then Intel brought out the new 6xx series chips that were re-engineered to accommodate 2megs of L2 cache, this was P4?s last push. lol still trying to keep the P4 alive, why bother ..


 
Normal cache memory is SRAM which is static memory using transistors instead of capacitors that DRAM uses. Capacitors must be refreshed often unlike transistors hold their value as long as a it recieves a constant supply of power which makes DRAM slower.
 
Originally posted by: RichUK
actually L3 cache like the one used on the Intel EE's, were just normal SD RAM, and did not run at te same clock rate as the L1, and L2 cache's, and therefore was pointless marketing, becasue the L3 cache was not quicker than the normal RAM being used.

O well who cares intel sucks 😛
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wow you're stupid. the access latency of EE L3 is less than 50 cycles, over 4 times faster than memory latency, and given P4 freqs, 50 cycles is very good for a 2MB cache at 130nm. and it certainly wasn't "SDRAM" (you meant 1T memory?), otherwise the latency would be on par with regular memory latency.... and the array size would be a heck of a lot smaller.

also, a large last level cache decreases bus requests and can compesate for a slower interface with memory. hence, it isn't useless.

next time, answer the question instead of being an (incorrect) fanboi... or just shut yer yap.

for the record, the point of large L3 caches is to accomodate certain datasets which tend to pop up in server workloads. thats why many server chips have swollen last level caches. consumer workloads usually don't need them; sometimes they harm performance due to lengthened latencies.
 
Originally posted by: RichUK
Originally posted by: stevty2889
The cache is basicly ram for the CPU. The L1 cache is where the information is stored just prior to being executed by the CPU, the L2 cache feeds the L1 cache. IE if there is some data that is needed, and it's not in the L1 cache, it looks to the L2 cache. If a cpu has an L3 cache, then it stores data as well, and will be looked at next if the L2 cache doesn't have what it's looking for. Then it will look to the ram. Each lvl of cache is slightly slower than the next, but still much faster than ram.
Click to expand...

actually L3 cache like the one used on the Intel EE's, were just normal SD RAM, and did not run at te same clock rate as the L1, and L2 cache's, and therefore was pointless marketing, becasue the L3 cache was not quicker than the normal RAM being used.

O well who cares intel sucks 😛
Click to expand...
No, L3 cache is not SDRAM, it is SRAM just like the rest of the cache, made up of transistors just like the rest..and it's still way faster than system memory.
 
Originally posted by: stevty2889
No, L3 cache is not SDRAM, it is SRAM just like the rest of the cache, made up of transistors just like the rest..and it's still way faster than system memory.
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well, 1T memory is also made of transistors LOL

because it was no quicker then the normal P4's, sometimes it was a tad but not enough to warrant 3 times the price).
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do yourself a favor and check out the performance delta of AMD's "premium" products and compare the prices... same deal as intel. sooner or later you'll figure out the real metric that decides prices... well, you might, since you're not too bright.
 
I believe Intel's cache is different from AMD's in that AMD's caches and memory function more like one big area of memory, but with faster sections, the L1 and L2. But with the Pentium 4, everything that's in the L1 cache is also in the L2, and everything in the L2 is also in the L3 if it exists, and everything there is also in RAM.
 
Originally posted by: Jeff7181
I believe Intel's cache is different from AMD's in that AMD's caches and memory function more like one big area of memory, but with faster sections, the L1 and L2. But with the Pentium 4, everything that's in the L1 cache is also in the L2, and everything in the L2 is also in the L3 if it exists, and everything there is also in RAM.
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all caches are contextual memories. from the pov of the cpu, a logical address just a reference to place somewhere in "flat memory". all processors still have memory hierarchies... you cannot have a L2 that doesnt talk to L1... well, you could, but it'd be a hell of a mess.

and the p4 caches are not write-through, they're writeback... a cache line can be clean in L1 but swapped out in L2.
 
Originally posted by: dmens
Originally posted by: Jeff7181
I believe Intel's cache is different from AMD's in that AMD's caches and memory function more like one big area of memory, but with faster sections, the L1 and L2. But with the Pentium 4, everything that's in the L1 cache is also in the L2, and everything in the L2 is also in the L3 if it exists, and everything there is also in RAM.
Click to expand...

all caches are contextual memories. from the pov of the cpu, a logical address just a reference to place somewhere in "flat memory". all processors still have memory hierarchies... you cannot have a L2 that doesnt talk to L1... well, you could, but it'd be a hell of a mess.

and the p4 caches are not write-through, they're writeback... a cache line can be clean in L1 but swapped out in L2.
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<a target=_blank class=ftalternatingbarlinklarge href="http://arstechnica.com/articles/paedia/cpu/amd-hammer-1.ars/9">The Hammer's L2, in contrast, does not share any data in common with the L1. Rather, cache blocks that are evicted from the L1 go into the L2...

... L1 and L2 act in concert as a very large L1 cache with a smaller, faster region (the actual L1) and a larger, slower region (the L2).</a>

If you don't read the article, the Hammer is being compared to the Athlon XP core... from what I read about the P4, it's like the Athlon XP core in terms of cache hierarchy. I could be mistaken...
 
i dont understand what the article is saying. obviously lines evicted from the L1 go to L2 and beyond on writeback, that happens with all caches. but that doesn't mean data exists exclusively on the L1 or L2. lines can still be read from L2 to L1 on a clean read and it would still be valid in both cache levels.

in addition, the article claims that cache hierarchies are data subsets. not true, because with writeback schemes, data can exist in the L1 as dirty valid while the same line in L2 has been swapped out.

describing hammer's L2 as a victim cache is also inappropriate. traditionally, victim caches are small, speedy buffer for evicted lines from fast caches, and it doesn't have to worry about dealing with other cache levels. technically, all caches that exist below another is a "victim cache" because it receives evicted lines... but it has much higher latencies and should be considered a seperate entity from a performance POV.
 
Originally posted by: dmens
i dont understand what the article is saying. obviously lines evicted from the L1 go to L2 and beyond on writeback, that happens with all caches. but that doesn't mean data exists exclusively on the L1 or L2. lines can still be read from L2 to L1 on a clean read and it would still be valid in both cache levels.

in addition, the article claims that cache hierarchies are data subsets. not true, because with writeback schemes, data can exist in the L1 as dirty valid while the same line in L2 has been swapped out.

describing hammer's L2 as a victim cache is also inappropriate. traditionally, victim caches are small, speedy buffer for evicted lines from fast caches, and it doesn't have to worry about dealing with other cache levels. technically, all caches that exist below another is a "victim cache" because it receives evicted lines... but it has much higher latencies and should be considered a seperate entity from a performance POV.
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I have an easier time understanding the article than I do you. I have no idea what you're trying to say.
 
OK Dmens i was mistaken about the memory, well to a certain extent anyway, and looking back i actually did mean to put SRAM/1T instead of SDRAM, anyways thanks for the info i am enlightened by you all, i always like to learn 😉 .. i stated that the L3 cache was not as good (speed wise) as the L1 and L2 caches on the EE, because i have read that on a review at THG (must have misread) .. anyways i am an AMD Fanboy that i can not deny 😀😀
 
Basically the A64s have exclusive caches while the P4s have inclusive caches. That's the difference that I think the article is trying to show. Exclusive caches mean that data in 1 cache level isn't duplicated in the other. When a L2 cache line is accessed twice with difference addresses, a swap will occur between the L1 and L2 rather than an L2->L1 copy. This effectively increases cache associativity, and the L2 cache is a victim buffer(different from a victim cache) for the L1 cache.

Also, AFAIK the P4 L1 dcache is write-through and the L2 cache is write-back. I'm pretty sure of this from the various Netburst architecture papers I've perused.
 
Originally posted by: RichUK
Originally posted by: Cheesetogo
What is the point of a level 3 cache?
Click to expand...

its because Intel quickly wanted to add more numbers (I.E. 2Mb Cache), to justify the extreme'ness of their 3.43 extreme edition over the 3.6 P4 out at the time. (Also they added the 1066 FSB all numbers again) pretty sad if you ask me. (because it was no quicker then the normal P4's, sometimes it was a tad but not enough to warrant 3 times the price).

Also they didn?t have the time to be able to re-engineer there chips or fab?s to accommodate 2Mb of L2 cache on the CPU die within a time scale they would have liked (competing with AMD's release), then Intel brought out the new 6xx series chips that were re-engineered to accommodate 2megs of L2 cache, this was P4?s last push. lol still trying to keep the P4 alive, why bother ..
Click to expand...

The 2MB of L3 cache was on the core, it was not an "added chip", and it is significantly faster than any DDR out today. The 130nm extreme editions were nothing more than Gallatin core xeons, which did take advantage of the extra cache (in a server environment). The cache did improve gaming performance on the EEs as well. While i would agree that it wasnt worth a $600 increase, it did make a difference.
 
Originally posted by: Goi
Basically the A64s have exclusive caches while the P4s have inclusive caches. That's the difference that I think the article is trying to show. Exclusive caches mean that data in 1 cache level isn't duplicated in the other. When a L2 cache line is accessed twice with difference addresses, a swap will occur between the L1 and L2 rather than an L2->L1 copy. This effectively increases cache associativity, and the L2 cache is a victim buffer(different from a victim cache) for the L1 cache.

Also, AFAIK the P4 L1 dcache is write-through and the L2 cache is write-back. I'm pretty sure of this from the various Netburst architecture papers I've perused.
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See now that makes sense. 😀
 
The whole point of multiple cache levels is to allow the most frequently used data to have the lowest access latencies while still providing relatively quick access to data less frequently used.
Processor cache is there so that the processors can avoid main memory access as much as possible, and so avoid the access penalties associated.
 
Originally posted by: roguerower
Thanks for all the replies. I take it that 2mb on L2 is better than 1mb. INTEL RULES.
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More cache is always better for performance, as long as the cache access latency remains the same. However, increasing cache size also increases hit time, which is why L1 caches are so small compared to L2 and L3. Also, increasing cache size increases leakage power as well as die area, which may be a problem in certain designs.
 
Originally posted by: Goi
Originally posted by: roguerower
Thanks for all the replies. I take it that 2mb on L2 is better than 1mb. INTEL RULES.
Click to expand...

More cache is always better for performance, as long as the cache access latency remains the same. However, increasing cache size also increases hit time, which is why L1 caches are so small compared to L2 and L3. Also, increasing cache size increases leakage power as well as die area, which may be a problem in certain designs.
Click to expand...

Thats not necessarily true I mean look at intel's Extreme edition processors with huge amounts of cache but no performance gain...
 
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