You know what, I think I was wrong in that other post then. They may be differentiating between the Data L1 cache and Instruction L1 cache. AMD use to do this, I guess they still do?
That would still explain the dual-core though...64KB data + 64KB instruction (per core) could be sold as 128KB (data) + 128KB (instruction)...
Each core has 64 KB of data cache and 64 KB of instruction cache. There are 2 cores. Confirmed here (search page for 1218). Newegg's way of expressing it is somewhat confusing, but still basically correct.
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