When you spend 3 hours trying to figure out what's wrong with your design, and it turns out that ncverilog is lying, your design is fine, Modelsim says everything works... Cadence's $monitor is just pulling numbers from some unrelated part of your design for no apparent reason. You also have to love it when cadence "vlog" compiles code fine and cadence "verilog" complains about syntax. :|
Of course, it's possible that it isn't really a bug, but some strange feature documented somewhere in the ~12 foot thick manual.... but normal humans don't have the time to read all of it 😉. I wonder if I should send them the code that produced the crazy behavior.
Of course, it's possible that it isn't really a bug, but some strange feature documented somewhere in the ~12 foot thick manual.... but normal humans don't have the time to read all of it 😉. I wonder if I should send them the code that produced the crazy behavior.
