Junctionless Gated-All-Around Carbon Nanotube Field Effect Transistors

[GWestphal]

Are these the be all, end all of FETs?

http://en.wikipedia.org/wiki/Carbon_nanotube_field-effect_transistor

CNTFETs show different characteristics compared to MOSFETs in their performances. In a planar gate structure, the p-CNTFET produces ~1500 A/m of the on-current per unit width at a gate overdrive of 0.6 V while p-MOSFET produces ~500 A/m at the same gate voltage.[23] This on-current advantage comes from the high gate capacitance and improved channel transport. Since an effective gate capacitance per unit width of CNTFET is about double that of p-MOSFET, the compatibility with high- k gate dielectrics becomes a definite advantage for CNTFETs.[21] About twice higher carrier velocity of CNTFETs than MOSFETs comes from the increased mobility and the band structure. CNTFETs, in addition, have about four times higher transconductance.

Pros:

Better Control over channel formation.
Better Threshold Voltage.
Better Subthreshold slope.
High Mobility.
High Current density.
High Trans-conductance.

Cons:
Scaling/Mass Production (non-existent)
Degraded by oxygen rapidly

My concern is that reliable, cheap manufacturing might not be possible and I'm not sure it's completely CMOS compatible.

For the foreseeable future, are Gated-All-Around Junctionless Hi-K Metal FETs a reachable Holy Grail? How would these compare to Intel's current Tri-Gate design? Does adding that 4th gate make a huge difference?

 

[William Gaatjes]

Interesting.
I am wondering how that increased capacitance would affect efficiency during switching and the speed of switching.

With classical discrete mosfets(and i would assume that the same principle applies for mosfets inside integrated circuits such as central processing units), the total gate charge given in a datasheets, is a simply put the combination of the gate source capacitance and the gate drain capacitance.
This total gate charge number defines how much current must be sinked and sourced from the gate (with respect to the source) of the mosfet in order to switch at a certain rate.
That is why when the frequency of switching increases, the power consumption increases because of I^2*R losses together with higher currents needed to discharge and charge all the capacitances faster.

For example :
A discrete mosfet build up of hundreds of mosfet cells such as from fairchild, . each only having a fraction of the total gate charge of the complete discrete mosfet. A very small amount of capacitance for every single mosfet cell that adds up with every cell added to increase maximum current and lower Rds on for the entire discrete mosfet..

From the 3D fet design of Intel, i get the impression that it is not the capacitance that is important, but the electric field that is created. I get the impression that the lowest possible capacitance together with the strongest desired electrical field is going towards ideal.

How must we see the electric field for a CNT fet ?