Ivytown info

[Phynaz]

Intel is presenting Ivytown at ISSCC this week. Here's the only info I've been able to find.

Ivytown packs 15 cores and 37.5 Mbytes shared L3 cache on an enhanced ring. The 4.31 billion transistor chip supports a one-PLL per column clocking structure and a multimode memory interface

 

[ShintaiDK]

The IB-EX. Amazing chip.

 

[Arachnotronic]

Intel is presenting Ivytown at ISSCC this week. Here's the only info I've been able to find.

Same transistor count as the 12 core IVB-EP. Looks like they're the same die...

 

[Homeles]

Same transistor count as the 12 core IVB-EP. Looks like they're the same die...

Where'd you get the 12-core transistor count? Do you happen to have info on the die size? I'd also kill for a die shot...

 

[Arachnotronic]

Where'd you get the 12-core transistor count? Do you happen to have info on the die size? I'd also kill for a die shot...

http://www.theregister.co.uk/2013/09/10/intel_ivy_bridge_xeon_e5_2600_v2_launch/

The top-end twelve-core Xeon E5-2600 v2 chip has around 4.3 billion transistors and has an area of 541 millimeters square. The Ivy Bridge-EP processors are going to pack a pretty big punch compared to the Sandy Bridge-EP processors they replace in the Intel lineup.

I can't get you a die shot of the EX, but it now makes perfect sense to me why Intel only showed off the 10 core IVB-EP wafers at IDF (yes, I got to see one up close and personal, and yes it was magical).

 

[ShintaiDK]

Isnt there only a 6, 10 and 15 die version? That would explain why the 12 and 15 may be same size and amount.

 

[NTMBK]

I'm not buying it- Intel flat out said that there was a 12-core E5 die.

And doesn't the E7 have a lot of RAS features the E5 doesn't?

EDIT: Plus according to (the ever reliable :\ ) Wikipedia, Ivy E7 goes up to octa-processor- I'd expect that would need more than 2 QPI links.