Ivy Bridge E to come in Q3 2013

[ShintaiDK]

Are you sure? Looks real enough to me, or at least not more fake than many real ones that were leaked before and called fake as well.

Editing the boxes, spellchecker, SB chips thats not supposed to be there, slapped around boxes, missing information etc.

It looks anything but real.

 

[coffeejunkee]

Yes, it's a screenshot of the slide in the process of being created/edited...author went to lunch, intern pressed prtscn and posted it.

But which SB chips are not supposed to be there? Those are not eol afaik.

 

[ShintaiDK]

Yes, it's a screenshot of the slide in the process of being created/edited...author went to lunch, intern pressed prtscn and posted it.

But which SB chips are not supposed to be there? Those are not eol afaik.

Sure....

I dont think Intel suddenly got a change of mind. And quadcore SBs are basicly EOL, already places where they cant be bought anymore.

 

[coffeejunkee]

Well, fake or not...the point is that there is not that much time left before Haswell comes out. Certainly not enough to eol current s2011 cpu's and introduce Ivy-E as successor. So it doesn't seem unlikely that we move to a situation where the highend is actually a generation behind. Which is completely opposite from the situation with s1366 cpu's.

Now I thought that Intel made loads of money by introducing high-end first. There were certainly a lot of i7 920 buyers who bought it despite high prices only because there was simply nothing else available. But maybe they missed more money from delayed midrange upgrades. Or it just has a technical reason.

 

[cbn]

when has a die shrink ever produced heat issues until now? This is a garbage excuse and people believe it. Learn to embrace a little conspiracy people.

According to this paper found on the Intel website it is something to consider.

V. SUMMARY AND IMPLICATIONS
The 30-year-long trend in microelectronics has been to increase
both speed and density by scaling of device components
(e.g., CMOS switch). However, this trend will end as
we approach the energy barrier due to limits of heat removal
capacity. For nanoelectronics, this result implies that an increase
in device density will require a sacrifice, due to power
consideration, in operational speed, and vice versa. Thus, it
appears that we are entering a regime where tradeoffs are required
between speed and density, quite in contrast to the
traditional simultaneous benefits in speed and density from
conventional scaling.

Looking forward to the new process techs Intel is developing to wrestle this problem away.

 

[ShintaiDK]

/sarcasrm: Oh noes, Core 2 is having a heat issue!

 

[cbn]

/sarcasrm: Oh noes, Core 2 is having a heat issue!

I like that graph a lot, but the Core 2 design is widely touted as being a lot more efficient than Netburst.

What we need is a more up to date graph showing the heat density progression over the last few years (eg, Ivy, Sandy, etc)

With that said, I am sure Intel will find a solution to the problem.