Is vDroop Like A Rubber Band?

[BonzaiDuck]

Other members here, in addition to me, have directed inquiring thread-posters to the Anandtech article by Kris Boughton of 12/19/2007 entitled "Overclocking Intel's New 45nm QX9650: The Rules Have Changed" as it pertains to the effects of load line calibration on the real upper limits of voltage in the load-to-idle transition:

http://www.anandtech.com/show/2404/6

Let us suppose that I used an upper limit of 1.37V in my over-clocking endeavors, so in using "Offset" mode, my full-load minimum voltage reaches 1.31V.

Let us also suppose that I am using the second-lowest LLC setting, and that I have determined that this setting would cause a voltage-overshoot above 1.37 to 1.39V, or a 0.02V overshoot. Such a determination was deduced from reviewing a table of actual results for the same motherboard and processor, giving the load-voltage increase as a result of selecting any one of the five possible LLC settings for the motherboard.

Whether I am correct in making this deduction is not so much an issue in answering my question, or if it is, it is only a factor.

Instead, consider two scenarios. In one scenario, I am heavily loading my processor, either in a stress-test or through some applied usage like "Folding" so that voltage droops to 1.31V. In the other scenario, I am only loading the processor lightly, as with some game which at most causes the voltage to droop to around 1.35V.

Since the overshoot and the idle stabilization at my 1.37V "target" is a matter of a harmonic fluctuation, am I correct to assume that the overshoot would be at maximum under the full-load situation, and something less for lightly-loaded situations?

In other words, is "vDroop" like a rubber-band?

 

[Idontcare]

Since the overshoot and the idle stabilization at my 1.37V "target" is a matter of a harmonic fluctuation, am I correct to assume that the overshoot would be at maximum under the full-load situation, and something less for lightly-loaded situations?

Yes.

The way in which LLC functions, electrically that is, is such that the magnitude of the overshoot when the system becomes "unloaded" is proportional to the magnitude with which the LLC electronics were compensating against Vdroop when the system was loaded.

In comparison to a more loaded system, a less loaded system would have resulted in less voltage compensation from the LLC circuitry, so when that less loaded system became an unloaded system the momentary overshoot from the LLC circuitry would be less as well.

 

[2is]

It sounds like LLC is the rubber band here and vdroop caused by loading is what's applying the tention

 

[BonzaiDuck]

Yes.

The way in which LLC functions, electrically that is, is such that the magnitude of the overshoot when the system becomes "unloaded" is proportional to the magnitude with which the LLC electronics were compensating against Vdroop when the system was loaded.

In comparison to a more loaded system, a less loaded system would have resulted in less voltage compensation from the LLC circuitry, so when that less loaded system became an unloaded system the momentary overshoot from the LLC circuitry would be less as well.

Thanks, IDC. I must have had an epiphany of intuition, and was actually looking for a response from someone with your background.

I'm thinking that a situation in which EIST is used or where "fixed-VCORE" OC'ing is not, the same logic still applies, except that the processor no longer spends perpetual idle time at the highest observable voltage.

ADDENDUM: Letting my intuition wander again, if we applied a rubber-band analog to LLC and vDroop under different loading conditions for "load-to-idle" transition, I'm wondering if the analog of a "ratchet" doesn't better apply to the "idle-to-load" transition.

 

[michaelrw]

rubber band works, though this rubber band doesnt always flex in both directions.. most of the time its unidirectional

 

[Smoblikat]

It would be less the less it is stressed.

 

[BonzaiDuck]

It would be less the less it is stressed.

But that's the point, as IDontCare confirmed.

After a year of stellar operation, I've doubled my memory and increased memory speed with minimal tweaks to the VCCIO voltage and near-spec RAM voltage. I am quite convinced that my 4.6Ghz (46 x 100) settings are slightly over-volted.

Yet I believe I'm operating at, below -- or ever so slightly above a very reasonable target -- prevalent multinationally as advised in forums and "guides."

So I'm trying to evaluate how day-to-day operation stresses the processor and causes voltage overshoots. I THINK I know what those overshoots are.

But if the processor is barely loaded, the overshoots are even less than that, minimal or insignificant.

I just need to set aside time to reduce one or two settings until I can get the system to fail in less than an hour, then find the stable setting again. I think I could be looking at a reduction between 0.01 and 0.02V.

Meanwhile . . . . I feel complacently "safe" for this processor. More than I need to, even . . .