thanks guys, I did a little research and found some math that backs up your claims. This could be interesting to some people (I was facinated!):
So every Intel processor has to go "outside" to access memory unlike AMD's built-in memory controller. And to access memory they have to go through the lanes connecting the processor to memory (connection pipe). Although you can crank up your memory to incredible bandwith but if this bandwidth exceeds the the bandwidth of the connection pipe then your CPU will not be able to access this extra bandwidth, in this case you are wasting the bandwidth and it is better to turn this extra bandwidth to lower latency. So let's do some math:
Bp = bandwidth of connection pipe between CPU and your memory (called the bus)
(1) Bp = FSB speed/1000 (in Ghz) * 64bits (bus width) * 4 (quad pumped) = FSB /1000 * 8bytes * 4 = FSB/1000 *32bytes
e.g: you running FSB = 300Mhz
Bp = 300/1000 * 32 = 9.6 Gbyte/sec bandwidth
Bm = the bandwidth of your memory
(2) Bm = RAM speed/1000 * 64bit (DDR2 bus width) * 2 (dual channel) = RAM spd/1000 * 8bytes * 2 = RAM spd/1000 *16bytes
e.g. you running at DDR800
Bm = 800/1000 * 16bytes = 12.8 Gbyte/sec bandwidth
thus we want (3) Bp >= Bm at all times this means the conecting pipe is wide enough to allow 100% of memory bandwidth to pass though to your CPU.
however say in the exmaple above if we are running 300 FSB and somehow using dividers (2.66) we get our memory to 800Mhz, then roughly 25% of your memory's bandwidth is unused at all. 12.8 total memory bandwidth output, but only 9,6 accesable to your CPU. You just wasted 25% of the bandwidth. Thus in order to get 100% of this 12.8 GB/sec bandwidth from the memory you need to run FSB at 400+ thus widening the connection pipe to 12.8 GB/sec enough to allow FULL memory bandwidth through.
These two little equations has an interesting implication:
so we want (3) Bp >= Bm substitue for each from equations (1)+(2) we get:
FSB/1000 *32bytes >= RAM speed/1000 * 16bytes
simplify we have:
2*FSB >= RAM speed
divide we get:
2 >= RAM-speed/FSB-speed
since we know RAM-speed/FSB-speed = the memory divider we use, this effectively means:
2>=memory divider
Put it simply we must use a memory divider smaller than 2 to not waste your memory bandwidth due to CPU-RAM pipeline limitation. Since on 965P all dividers are 2 or higher, we can confidently say the optimal divider=2 on 965P. Any higher divier will allow higher RAM speed with no conceivable benefit to the CPU whatsoever. This also means after keeping divider at 2, you want to use as high a FSB as possible for your RAM. So for say E4300 using a lower divider like 8 instead of 9 can push up the FSB a bit and achieve higher memory bandwidth for your CPU (provided you use memory divider of exactly 2 for 965P). If your bandwidth gets ahead of connecting pipe bandwidth then it's time to trade that wasted bandwidth for lower latency.
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