Is EUV Fab being pushed out again?

[Viditor]

Semi Int article

"The idea, Wood said, is for EUV to be put to work at the 15 nm scale sometime around 2013-2014, with serious process development taking place about two years before that. Although EUV lithography had been originally slated for 65 nm half-pitch, its production entry has continually slipped largely because of readiness issues with sources, masks, resists and more. At the same time, optical lithography continued to advance to the point where EUV was not really needed at such an early timeframe. Now, however, as chipmakers look to the 22 nm node, there is question about what technologies will be available for use on critical layers, including concerns about the cost of double patterning, a lack of support for high-index immersion lithography, and the production readiness of EUV. Many in the industry are saying that EUV will likely not be ready for insertion until the 16 nm node, and others are saying it may never be ready"

Edit: One question that occurs to me...with EUV possibly being pushed to 15nm, does that mean that tick-tock will slow down?

 

[soccerballtux]

Nobody can predict the future. If it's not ready then we may just have to sit around for a bit. Might give AMD some chance to catch up!

 

[Idontcare]

Originally posted by: Viditor
Edit: One question that occurs to me...with EUV possibly being pushed to 15nm, does that mean that tick-tock will slow down?

It's a fair question. The EUV timeline push-out is quite similar to that of the projected adoption of ULK dielectrics. ULK, much like with EUV, are not the only way to skin the cat...rather they are viewed as ultimately the best way to skin the cat at some point in time in the future so why not adopt the technology at the earliest feasible point in time and avoid wasting resources on the alternatives that are viewed as being guaranteed to be supplanted by EUV/ULK eventually anyways.

As we saw with ULK though (k = 2.2, originally viewed as necessary for 65nm) the intermediate alternatives turned out to be cheaper, less complicated, more robust for manufacturing environments, etc and so they were implemented (and resourced for implementation) at the expense of escalating the development and implementation of ULK's.

Same for lithography. Once 193nm immersion litho gained credibility in the R&D realm around 2004 it completely undermined the 157nm dry litho efforts as well as EUV. Make no bones about it, every R&D dollar that went to developing immersion litho was an R&D dollar that got taken away from EUV, making its timeline push-out a self-sustaining Sisyphus project. Same as ULK.

But these guys who get interviewed to talk about EUV have no choice but to make the situation out to be as dire and as imperative to the industry as they possibly can...if they don't then its their own jobs that are on the line (at worst) or next year's budget will be reduced (at best). Ask a GM worker in Detroit if the American auto industry is vital to the US economy and you'll get the expected answer, ask a Toyota worker in the south if GM is vital to American auto industry and you'll get an entirely different answer. (add necessary computer/car analogy, check)

Back to the original question, I doubt tick-tock will slow down (ever) for reasons of technical engineering challenges...the slowdown will be solely financial driven as the reducing ROI for creating each new node shrink has the knock-on effect of reducing the R&D budget for creating the next node shrink (which itself will in turn be more expensive to develop and manufacture).

Hence the continual shrinking of the pool of R&D CMOS process development companies out there.

 

[IntelUser2000]

The thing is semi-revolutionary steps like EUV/Copper/Hi-K/Immersion is good when you do it, but if you can live without it there are benefits to it. According to Realworldtech, Immersion machines can cost up to $28 million per unit, but since Intel is the only company using complete dry lithography at 45nm, they potentially save money there(and there was a Semiconductor Insight article saying about Intel's how their mask costs are lower than others).

Intel is supposed to be using immersion lithography at 32nm, but only at the critical layers. Who knows, by the time we get to 2015, something other than EUV might be another road to go for.

 

[Viditor]

Originally posted by: IntelUser2000
The thing is semi-revolutionary steps like EUV/Copper/Hi-K/Immersion is good when you do it, but if you can live without it there are benefits to it. According to Realworldtech, Immersion machines can cost up to $28 million per unit, but since Intel is the only company using complete dry lithography at 45nm, they potentially save money there(and there was a Semiconductor Insight article saying about Intel's how their mask costs are lower than others).

Intel is supposed to be using immersion lithography at 32nm, but only at the critical layers. Who knows, by the time we get to 2015, something other than EUV might be another road to go for.

I am dubious that they're saving money on dry at this point...
While it's true that they save money on the tools, to do that they must use double patterning (which takes twice as long). It is an interesting question as to which is more expensive in the long run...

Originally posted by: Idontcare
Back to the original question, I doubt tick-tock will slow down (ever) for reasons of technical engineering challenges...the slowdown will be solely financial driven as the reducing ROI for creating each new node shrink has the knock-on effect of reducing the R&D budget for creating the next node shrink (which itself will in turn be more expensive to develop and manufacture).

Hence the continual shrinking of the pool of R&D CMOS process development companies out there.

I agree with your excellent post IDC, but isn't this sort of a chicken and egg point at the end? "Costs increase as technical challenges increase" I consider to be axiomatic...

So if Tech Challenges = Cost increases = reduced ROI = node shrink slowdown, then wouldn't saying "tech challenges" = "node shrink slowdown" be as correct (or am I missing something...?)
Again though...great post there...I especially appreciated the analogies as they were very clarifying for me.

 

[Idontcare]

Originally posted by: Viditor
I agree with your excellent post IDC, but isn't this sort of a chicken and egg point at the end? "Costs increase as technical challenges increase" I consider to be axiomatic...

I believe we have differing viewpoints here owing to a difference in our of definition of "technical challenge".

Some people view a "technical challenge" as ceasing to be a challenge once a technical solution is developed, regardless of the TCD (total cost of deployment) of that solution once implemented into manufacturing.

Other people take the view that part of the technical challenge is to not only develop a technical solution to the physics of the problem (how to print sub-32nm half-pitch features?) but to also generate a solution for which the TCD is the acceptable (does it add $100 per wafer pass to the manufacturing cost?).

It is the projected TCD envelope (which itself has a time component) of competing technical solutions that determines the funding priorities at the R&D level.

Intel for example had to decide in 2005 how they were going to print their 70nm half-pitch features for their 45nm node when it went to manufacturing in 2007. In 2005 the projected cost of deploying 193nm immersion scanners in 2007 time-frame were excessive compared to the cost of deploying 193nm dry scanners but losing about half the wph at the critical levels owing to double-patterning.

So in the 2005 time-frame Intel pulled the trigger to allocate their R&D dollars so as to prioritize implementing a double-patterning integration flow with the expectation that come 2007 and 2008 the total cost (when all things were factored, tool cost, fab space cost, wph impact, yield impact from D0, etc) of deploying double-pattern would be less than deploying immersion in the same time-frame.

So there are challenges - "how do we print 22nm half-pitch features?" - and then there are technical challenges - "how do hedge our bets today as to which possible litho solution will deliver us the lowest cost of deployment for manufacturing when we are printing 22nm half-pitch features in manufacturing in 2013?".

The latter question is what determines whether EUV gets prioritized for funding over alternative litho technologies such as imprint litho or some souped up version of high-RI immersion litho combined with next-gen computational lithography today for expected integration into 22nm node already a solid year into the development phase at this point in time.

Originally posted by: Viditor
So if Tech Challenges = Cost increases = reduced ROI = node shrink slowdown, then wouldn't saying "tech challenges" = "node shrink slowdown" be as correct (or am I missing something...?)

You have it correct if you look at it in an alternative viewpoint. The cadence for developing leading edge process technology has not changed really and it won't, but it does get more expense to develop the technology and even more deleterious it does get more expensive to manufacture low-volume chips on the technology because the mask sets pretty much double in cost for every new node.

So what is slowing down is the cadence of products making the migration to newer nodes when the new nodes become available.

I'm not talking about the 6-10 super high-volume chips you and I follow as enthusiasts (AMD, Intel, ATI, NV, plus the DDR/NAND chips) but rather I am talking about the other 75% of the semiconductor industry that is basically still producing sellable chips at 90nm and larger.

Checkout revenue by technology stats for Q408 on TSMC here: http://www.tsmc.com/uploadfile...erly/business_info.xls

73% of their revenue is still generated by 90nm and larger IC's.

Has node development cadence slowed down? Not really. Has node adoption slowed down? Absolutely.