MadRat
Lifer
Apparently DDR|| will be faster memory than DDR and SDR because it will be built on a smaller die, hence its use of 1.8v versus DDR's and SDR's 2.5v. But because DDR|| is essentially quad-interleaved SDRAM there will be an extra two cycle or more of latency across the bus for data transfers as compared to the older SDR. This is going to be slowing down the "quickness" of the memory for a potentially larger bandwidth. Does that mean that DDR||| will be octi-interleaved SDRAM with a four cycle latency for each transfer?? We seem to be adding a necessary time element to these types of memory as the technology develops.
The Pentium4, because it already has a long latency on cache misses but compensates with a relatively huge cache, doesn't rely on the quickness of the memory so much as the bandwidth of it. I'm guessing that speeds of the RAM will have to be 5-15% faster for DDR|| to catch up to the transfer latency of older DDR memory although it will enjoy potentially twice its bandwidth. Sounds like a fair trade for CPUs with large L1/L2 caches, but won't this trade off really penalize processors that cut down the size of their internal caches? Celeron and Duron would likely be choked by this trend in the technology. The chasm between "Celeron" and "Pentium" will likely be so large that they'll need equal speed Celerons to be within 50% of the performance...
I'm guessing that if memory latencies keep escalating like they do with each successive generation then a level 3 cache will be more worthwhile for low and high end machines alike. The future of DDR (|| and |||) seem to be penalizing the lower cache processors to the point of irrelevance.
The Pentium4, because it already has a long latency on cache misses but compensates with a relatively huge cache, doesn't rely on the quickness of the memory so much as the bandwidth of it. I'm guessing that speeds of the RAM will have to be 5-15% faster for DDR|| to catch up to the transfer latency of older DDR memory although it will enjoy potentially twice its bandwidth. Sounds like a fair trade for CPUs with large L1/L2 caches, but won't this trade off really penalize processors that cut down the size of their internal caches? Celeron and Duron would likely be choked by this trend in the technology. The chasm between "Celeron" and "Pentium" will likely be so large that they'll need equal speed Celerons to be within 50% of the performance...
I'm guessing that if memory latencies keep escalating like they do with each successive generation then a level 3 cache will be more worthwhile for low and high end machines alike. The future of DDR (|| and |||) seem to be penalizing the lower cache processors to the point of irrelevance.
