Nope I can't, but it is something like
2-3-3-3-3
vs
3-3-3-3-3
Basically memory now accesses multiple rows at once, typically 4. The column is only one delay, the row is another.
So we are talking 15 cycles vs 14 cycles (assuming it takes 3 cycles to pump a row back.) I've no clue how many cycles it really is. Different memories have differnt timming. Burts DRAM shaved a cycle of the row, I believe at the expense of the column. I forget what SDRAM does.
Perhaps CAS2 is 7-8% faster than CAS3, but then there are two levels of caching. So rominl's 3-4% sounds good to me
Moohoo