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Is anyone here handy with Pspice and output stages?

R

RaynorWolfcastle

Diamond Member
We designed a class B output stage and my simulations in pspice really aren't working out. The TA chose this dirty design in which there is a gain and the output stage connects to a transistor's emitter. Basically, we have to design the collector voltage to be at ground with no input voltage and my simulations aren't working out.

Someone please tell me a funny joke to get my mind off this. 🙁
 
So I walked into a bar one day, and as I stepped in, a girl looked at me and said "Nine" to her friend. I was feeling pretty good about being rated a nine out of ten, until I went to say hi to her and she replied "Guten Tag".
 
Originally posted by: TheLonelyPhoenix
So I walked into a bar one day, and as I stepped in, a girl looked at me and said "Nine" to her friend. I was feeling pretty good about being rated a nine out of ten, until I went to say hi to her and she replied "Guten Tag".
Click to expand...

Took me a few seconds but finally got it 😀
 
i've used PSpice a little before, but i can't really help you with that description. Are you sure it's all hooked up correctly and that you're running the correct sweep?
 
Originally posted by: Stojakapimp
i've used PSpice a little before, but i can't really help you with that description. Are you sure it's all hooked up correctly and that you're running the correct sweep?
Click to expand...

Yeah, pspice isn't the problem., I know how to use it properly. I'm not really looking for help, I was going to ask for help but then decided that I just needed a change of ideas.
 
spice is worse than any programming language can ever be. Have you ever looked at the models used by spice? They're friggin incomprehensible by everyone except for maybe the people who write them. The smaller the dimensions of the transistor, the more incomprehensible the models become. Level 7 models are just plain gibberish.
 
You using capture to draw the schematic, or entering the netlist by hand?

If the latter, make sure you have 0 as the ground, otherwise pspice will get pissed.

Oh, and your output stage is in a "grounded collector" configuration... and it will have huge gain, unless you wrap some feedback around it.
 
Originally posted by: blahblah99
You using capture to draw the schematic, or entering the netlist by hand?

If the latter, make sure you have 0 as the ground, otherwise pspice will get pissed.

Oh, and your output stage is in a "grounded collector" configuration... and it will have huge gain, unless you wrap some feedback around it.
Click to expand...

The circuit is fine, I'm entering the netlist by hand but that's not the problem.

The collector isn't actually grounded, it has to be set up so that the darlington pairs that form the output stage are connected so that when there's no input signal, there's no output signal. There's no feedback for this portion of the circuit.

The problem is that because they want us to use f@#@ing gain in an output stage we have to connect the collect of a transistor that provides gain to an output stage. Furthermore, since it's a class B output stage that's not in active mode, we have to use the exponential relationship to find the correct bias points.

All in all, it's just a pain in the ass.

edit: also, without going into further details they set a bunch of conditions on gain, bandwidth, and quiescent currents that make it even more of a pain to work with.
 
Originally posted by: RaynorWolfcastle
Originally posted by: blahblah99
You using capture to draw the schematic, or entering the netlist by hand?

If the latter, make sure you have 0 as the ground, otherwise pspice will get pissed.

Oh, and your output stage is in a "grounded collector" configuration... and it will have huge gain, unless you wrap some feedback around it.
Click to expand...

The circuit is fine, I'm entering the netlist by hand but that's not the problem.

The collector isn't actually grounded, it has to be set up so that the darlington pairs that form the output stage are connected so that when there's no input signal, there's no output signal. There's no feedback for this portion of the circuit.

The problem is that because they want us to use f@#@ing gain in an output stage we have to connect the collect of a transistor that provides gain to an output stage. Furthermore, since it's a class B output stage that's not in active mode, we have to use the exponential relationship to find the correct bias points.

All in all, it's just a pain in the ass.

edit: also, without going into further details they set a bunch of conditions on gain, bandwidth, and quiescent currents that make it even more of a pain to work with.
Click to expand...



Haha, well thats not a pspice problem, that's a design problem! 😉
 
Originally posted by: blahblah99
Haha, well thats not a pspice problem, that's a design problem! 😉
Click to expand...
it becomes a spice problem when the hand calculations competely fail/become too complicated and you're randomly entering numbers hoping that things will work out. 😛


Have you ever felt like being an EE student is like getting kicked in the pants except that the pain lasts 4 years instead of a few minutes?
 
Originally posted by: RaynorWolfcastle
Originally posted by: blahblah99
Haha, well thats not a pspice problem, that's a design problem! 😉
Click to expand...
it becomes a spice problem when the hand calculations competely fail/become too complicated and you're randomly entering numbers hoping that things will work out. 😛


Have you ever felt like being an EE student is like getting kicked in the pants except that the pain lasts 4 years instead of a few minutes?
Click to expand...

Been there. Done that. Except the pain lasted more than 4 years for me.
 
Originally posted by: RaynorWolfcastle

Have you ever felt like being an EE student is like getting kicked in the pants except that the pain lasts 4 years instead of a few minutes?
Click to expand...

That goes in my sig. :-D
 
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