IPC

[Nothingness]

No, a core that is faster (in GHz) may have higher ST performance, but not necessarily higher IPC.

In general, for a given core, the higher the frequency is, the lower the IPC is since memory latency (when measured in clock cycles) will increase.

 

[crashtech]

In general, for a given core, the higher the frequency is, the lower the IPC is since memory latency (when measured in clock cycles) will increase.

Yes, this is an important point to note with a given core. That's partly why performance increases don't scale linearly with clock speed, especially higher OCs.

 

[Headfoot]

exactly, IPC is a vague term in practice.
Are there any de facto standard how to measure IPC out there?

If by "in practice" you all mean how speculators in forums with no experience or working knowledge of the semiconductor design industry use it, then sure maybe its vague. But because people don't know anything about IC design use it incorrectly doesn't change what it means...

 

[ElFenix]

OP is the only person here who is confused as to what IPC is.

Which is the same.

You could also say instructions per clock cycle.

no, that's intergovernmental panel on climate change

 

[teejee]

If by "in practice" you all mean how speculators in forums with no experience or working knowledge of the semiconductor design industry use it, then sure maybe its vague. But because people don't know anything about IC design use it incorrectly doesn't change what it means...

??
You don't need to know much about semiconductor design to understand the IPC concept, it only concerns the performance of a CPU per clock cycle.

My question was, how do you define and measure IPC? Different instruction sequences with same number of instructions can have very different execution time. You basically need a benchmark to define and/or measure IPC, but what benchmark?

 

[jhu]

Ice creams per clown

 

[TuxDave]

??
You don't need to know much about semiconductor design to understand the IPC concept, it only concerns the performance of a CPU per clock cycle.

My question was, how do you define and measure IPC? Different instruction sequences with same number of instructions can have very different execution time. You basically need a benchmark to define and/or measure IPC, but what benchmark?

I'm not really sure what you're asking. The upper bound of a CPU's IPC is going to be its allocation/retirement width and the lower bound of IPC is something closer to 0. And as you mentioned, the actual IPC you will get depends on the workload/program/benchmark. So it's impossible to have a benchmark that will give a single IPC number that's equal to the IPC for every workload out there.

 

[teejee]

I'm not really sure what you're asking. The upper bound of a CPU's IPC is going to be its allocation/retirement width and the lower bound of IPC is something closer to 0. And as you mentioned, the actual IPC you will get depends on the workload/program/benchmark. So it's impossible to have a benchmark that will give a single IPC number that's equal to the IPC for every workload out there.

Headfoot's post I responded to said that IPC is just a vague term for amateurs at forums like this, but something that people how know much "about design IC" knows more about.
So I wanted to know what he meant.

To me IPC is a general vague term, meaning intructions per clock without further definition.

I remember my old Amiga 500 where integer multiply took more than 50 cycles and integer division even more 🙂
So really bad IPC in some of my Amiga code....