- Feb 3, 2001
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I just learned this yesterday:
Propagation delay through a cmos inverter (and by extension, other typical cmos gates), is proportional to 1/(V_s - V_t) where V_s is the supply voltage and V_t is the threshold voltage for the transistors.
Why this might interest you:
Let's say you're overclocking your athlon, p4, or whatever. It's getting hot, so you turn down the supply voltage. Well, you've just raised the time required for the logic gates to switch between states, and at the same time, reduced the clock period - their margin or error for finishing the transition. If this is taken too far, then errors will result because the logic signas haven't had time to propagate property through the chip. Even if we weren't overclocking, we could turn the supply voltage down so close to the threshold voltage that the transition could literally take seconds.
I always wondered in the back of my head why you needed to turn up the voltage when overclocking, and now I've got actual equations to tell me. The intuition rests on the foundation of the cmos gate being a rather complicated RC low pass filter.
Propagation delay through a cmos inverter (and by extension, other typical cmos gates), is proportional to 1/(V_s - V_t) where V_s is the supply voltage and V_t is the threshold voltage for the transistors.
Why this might interest you:
Let's say you're overclocking your athlon, p4, or whatever. It's getting hot, so you turn down the supply voltage. Well, you've just raised the time required for the logic gates to switch between states, and at the same time, reduced the clock period - their margin or error for finishing the transition. If this is taken too far, then errors will result because the logic signas haven't had time to propagate property through the chip. Even if we weren't overclocking, we could turn the supply voltage down so close to the threshold voltage that the transition could literally take seconds.
I always wondered in the back of my head why you needed to turn up the voltage when overclocking, and now I've got actual equations to tell me. The intuition rests on the foundation of the cmos gate being a rather complicated RC low pass filter.
