Discussion Intel's past, present and future

[igor_kavinski]

40% improvement per clock at 13mm2, which is basically triple Lion Cove, while being clocked lower.

If it was such a failure, why would investors back Ahead Computing? Is it normal for venture capitalists to get behind people ousted for being abject failures?

 

[DavidC1]

If it was such a failure, why would investors back Ahead Computing? Is it normal for venture capitalists to get behind people ousted for being abject failures?

Meet Theranos: https://www.investopedia.com/articles/investing/020116/theranos-fallen-unicorn.asp

It's commonly said 90% of startups fail, and out of that, half are just treading water. So only 5% actually make money.

Even if the team had really good ideas, it's another thing to make it into something that is a genuine advancement in the real world.

 

[igor_kavinski]

Meet Theranos: https://www.investopedia.com/articles/investing/020116/theranos-fallen-unicorn.asp

I know about that but the people behind Ahead Computing are not total kooks like the Theranos nutcase.

My sense is that they were disrespected because certain people felt threatened by their work and they had no choice but to leave. When has Intel ever given a real reason for anyone leaving? We still have no official good reason for Jim Keller leaving. It's all internal politics.

 

[DavidC1]

I know about that but the people behind Ahead Computing are not total kooks like the Theranos nutcase.

They don't have to be. Computer chips advance at a breakneck pace. You aren't competing with whatever is out there now. You have to beat whatever is out there 5-6 years from now, whenever your project is done. And they fail.

If some people aren't willing to embrace ARM's way superior chips because of the codebase difference, why would you do the same with Ahead Computing's chip? This assumes they can achieve what they can achieve.

And until they were revealed investors didn't think Theranos people were kooks either.

 

[igor_kavinski]

And until they were revealed investors didn't think Theranos people were kooks either.

I was writing more when you replied. Point is, almost every reason behind Intel's failure is politics. The bad kind.

 

[Io Magnesso]

I don't think Granite Rapids is bad.
In fact, it's okay when it's single socket.
It seems that it is not able to scale well with dual sockets.
Well, even so, the gap with the tragic EPYC a few years ago has narrowed.
The difference in the number of cores, which was one of the challenges at the time, is almost non-existent now.

 

[Joe NYC]

I'm just going off of what Intel said at the Goldman Sachs conference a year or two ago.

RPL-H is a ~260mm2 die. PTL itself has a total die area of similar magnitude, and I would imagine NVL-H with the same core count won't differ much either.
The expensive packaging is the sticking point then, but Intel has had foveros in MP for what, 3 years by the time NVL comes out? I think Intel has both the volume and expertise atp with foveros where they feel like the cost is not a deal breaker.
I think you can also kinda sense it in Intel's earnings calls, they talk about the cost of using external primarily, followed by MoP for LNL specific, but throughout their earning calls they don't really talk about how margins are getting negatively impacted by using advanced packaging.

It is kind of curious that no one is talking about the packaging Intel chose for ALL of its current and future products. Because if it is sub-optimal, it would mean admitting all of Intel's products have an Achiles Heel.

When I asked Grok to compare costs of TSMC CoWoS and InFO, Grok estimate is CoWoS is 7x cost of InFO. And as I said, the Foveros technology Intel is using most closely resembles CoWoS.

What do you think the perf gap would be in 2028, against AMD?

Let's say on high performance chips (server, high end desktop), AMD may currently have 10% lead, and by 2028, there will be 2 generations, and suppose each one widens the gap by 10%. Which would be 33% overall.

In Gaming, AMD is starting with much wider gap, as much as 30% vs. Arrow Lake.

 

[Io Magnesso]

I know about that but the people behind Ahead Computing are not total kooks like the Theranos nutcase.

My sense is that they were disrespected because certain people felt threatened by their work and they had no choice but to leave. When has Intel ever given a real reason for anyone leaving? We still have no official good reason for Jim Keller leaving. It's all internal politics.

Jim Keller is for his own convenience
In the first place, Jim Keller was the vice president of the organization, and he may have been indirectly involved with advice on each project.
but I don't think Keller has ever created an architecture.
I think Jim Keller was mainly in charge of Chiplet and Interconnect.

 

[Geddagod]

You sure Griffin Cove will offer Tock like improvements when they did what they did on Lion Cove and Pantherlake will be 0%?

If Exist50 is right, which he often is, I imagine so. It's not out the the realm of possibility either, if Griffin Cove is actually "looting RYC's corpse" for ideas, and if the P-core team felt like it was their last ditch effort to stop either Royal Core or the E-core from replacing them, which ended up being unsuccessful.
I think the timelines can match up for this narrative to be the case. But, obviously, lots of speculation here lol.

We thought GNR would improve competitiveness, but they don't seem to be hugely closer compared to Emerald Rapids. In hindsight, EMR did fairly well. Of course, lot of GNR's disappointment is due to puzzling lack of scaling.

I wouldn't be taking Phoronix's geomeans with much confidence.
AMD's own slides have GNR competing with at the very least, Turin Standard.

Meanwhile this was EMR vs Genoa:

GNR seems to suffer due to the per-core performance not being very competitive since it uses RWC vs AMD on Zen 5. That issue should also be fixed to an extent with DMR too.

Intel 7 might be more expensive in unit cost, but it has higher volume since it was all Intel. 18A isn't.

Maybe. I think Intel projects margins improving though, and their 18A volume isn't insignificant either since they are making low end, high volume products on their own internal nodes.
I don't think Intel is in a bad situation margins wise with 18A.

 

[DavidC1]

When I asked Grok to compare costs of TSMC CoWoS and InFO, Grok estimate is CoWoS is 7x cost of InFO. And as I said, the Foveros technology Intel is using most closely resembles CoWoS.

Is Grok actually right though?

 

[igor_kavinski]

but I don't think Keller has ever created an architecture.
I think Jim Keller was mainly in charge of Chiplet and Interconnect.

He used to be a "get down and dirty" architect but his recent roles have been more akin to being an "engineering teams" manager.

 

[igor_kavinski]

If Exist50 is right, which he often is, I imagine so. It's not out the the realm of possibility either, if Griffin Cove is actually "looting RYC's corpse" for ideas, and if the P-core team felt like it was their last ditch effort to stop either Royal Core or the E-core from replacing them, which ended up being unsuccessful.

That does sound like the conniving P-core team...

 

[Joe NYC]

Is Grok actually right though?

Here is partial answer (estimate) cost per mm2, but in further discussion, Grok said there is a range of estimates:

Gather Cost Estimates from Sources:

• For CoWoS: Industry analysis indicates a cost of about 7 cents per square millimeter, driven by the silicon interposer and its associated processing steps. This is substantiated by TSMC's packaging evolution reports, where CoWoS is positioned for high-performance computing (e.g., AI accelerators) but noted as expensive.
• For InFO: Developed as a lower-cost alternative to CoWoS, InFO targets around 1 cent per square millimeter to meet customer demands for affordable packaging in consumer markets (e.g., Qualcomm's willingness-to-pay threshold for similar technologies). This is inferred from the same reports, where InFO replaces the silicon interposer to reduce unit costs while sacrificing some connection density and bandwidth.

BTW, way back, when I raised high cost of 2.5D Foveros to Exist50, when he was still around, he dismissed it...

 

[Geddagod]

40% improvement per clock at 13mm2, which is basically triple Lion Cove, while being clocked lower.

So you know the criticism against the P cores vs E cores? Now repeat that, except the P is Royal Core, and the E is Lion Cove.

The perf improvement was supposedly 40%, the IPC was supposedly double.
The biggest contention of the P-cores isn't even area (though that is bad), it's the equally bad power consumption.
Area is arguably the least important part of the PPA consideration, and Apple's very large cores should be a real life example that if a core is large, much better perf and power could make it viable.
With IPC that high and clocks looking to be that low, the power efficiency of this core likely would have blown anything else away. I imagine in server it would esentially be running at Vmin at extremely high perf/watt.
Further iterations of RYC were supposedly going to improve perf/mm2, but even the rumor iteration sounds like it would be viable enough...

And from what we hear, RYC was indeed a failure. I meant hail mary as in Core 2/Ryzen.

I'm guessing it was less engineering decisions that caused RYC to be canned, but financial and political ones.

I think the PTL's Compute Tile has a single area of 114mm.

Yes, I was referring to PTL's die area of all the tiles.
Actually, looking back at that document leak, PTL's active tile area is only ~220mm2.

Meet Theranos: https://www.investopedia.com/articles/investing/020116/theranos-fallen-unicorn.asp

It's commonly said 90% of startups fail, and out of that, half are just treading water. So only 5% actually make money.

Even if the team had really good ideas, it's another thing to make it into something that is a genuine advancement in the real world.

Surprising then Jim Keller joined the board of that company, despite also being the CEO of another risc-v company that also is aimed to produce high performance risc-v cores.
Given his history with Intel, I would imagine he had to seriously believe in the viability of the core and the people behind it in order to do this.

It is kind of curious that no one is talking about the packaging Intel chose for ALL of its current and future products. Because if it is sub-optimal, it would mean admitting all of Intel's products have an Achiles Heel.

Idk how much of ARL's problems coming from the packaging being suboptimal, vs the fabric itself just being very bad. We might see in NVL ig.

Let's say on high performance chips (server, high end desktop), AMD may currently have 10% lead, and by 2028, there will be 2 generations, and suppose each one widens the gap by 10%. Which would be 33% overall.

Current, LNC and Zen 5 have similar 1T perf.
In 2026 with Zen 6, Lets say NVL ST is only 10% better than ARL, and Zen 6 is 30% better than Zen 5, through some combination of IPC and Fmax improvements. Would be a very large 20% gap.
In 2027 lets say Griffin Cove is still only another 10% improvement over Cougar? Panther? whatever NVL's P-core is. They are now ~10% behind AMD.
In 2028 Zen 7 and hopefully unified core would be out. ~10% is the gap that Intel will be facing, spit balling a pretty bad case for Intel.

BTW, way back, when I raised high cost of 2.5D Foveros to Exist50, when he was still around, he dismissed it...

I mean you could still talk to him on reddit lol, he is active there...

 

[Joe NYC]

Current, LNC and Zen 5 have similar 1T perf.

I think that may be the case in "client productivity" applications.

But in server / workstation / desktop gaming, the gap is quite wide.

According to Phoronix, Arrow Lake trails 9950x by 18% and 9950x3d by 21%. Gaming is as much as 30%. Which is why I rounded to average 10% lead as a safe starting point.

You may get instances of LNC and Zen 5 having similar 1T performance, but that is with P cores that are too big and too hot. Which is what makes them a dead end (in eyes of Intel).

 

[Joe NYC]

I mean you could still talk to him on reddit lol, he is active there...

I would likely get banned there by the trigger-happy Intel Reddit moderators in a nanosecond, so no point...

 

[johnsonwax]

Ok thanks. Given that a TSMC 2nm fab costs $28 billion (estimate). Intel has $20 billion on hand right now. How do you think Intel can make a 16A fab?

Worth noting that TSMC didn't have to pay $28B. Anyone who wanted to reserve volume had to pay up front. A lot of that $28B came from Apple, etc. Cashflow solves a lot of funding problems. Apple typically runs upward of $40B in prepayments across their supply chain which buys a lot of manufacturing capacity. Intel would operate the same way, but with the challenge that whoever is making that investment has to have faith that Intel will be able to deliver. That's a big part of the current problem - customers are going to want a discount because Intel is unproven as a foundry (and is known for having a haughty attitude toward customers), and Intel can't really afford a discount. Federal programs can only carry you so far.

 

[Io Magnesso]

He used to be a "get down and dirty" architect but his recent roles have been more akin to being an "engineering teams" manager.

Well, it was a good experience for Jim Keller himself to have the experience of becoming a vice president of an Intel team before he set up an independent TT. I personally think so
Jim Keller has led a team in the past, but he's never led such a big team.

 

[Io Magnesso]

The perf improvement was supposedly 40%, the IPC was supposedly double.
The biggest contention of the P-cores isn't even area (though that is bad), it's the equally bad power consumption.
Area is arguably the least important part of the PPA consideration, and Apple's very large cores should be a real life example that if a core is large, much better perf and power could make it viable.
With IPC that high and clocks looking to be that low, the power efficiency of this core likely would have blown anything else away. I imagine in server it would esentially be running at Vmin at extremely high perf/watt.
Further iterations of RYC were supposedly going to improve perf/mm2, but even the rumor iteration sounds like it would be viable enough...

I'm guessing it was less engineering decisions that caused RYC to be canned, but financial and political ones.

Yes, I was referring to PTL's die area of all the tiles.
Actually, looking back at that document leak, PTL's active tile area is only ~220mm2.

Surprising then Jim Keller joined the board of that company, despite also being the CEO of another risc-v company that also is aimed to produce high performance risc-v cores.
Given his history with Intel, I would imagine he had to seriously believe in the viability of the core and the people behind it in order to do this.

Idk how much of ARL's problems coming from the packaging being suboptimal, vs the fabric itself just being very bad. We might see in NVL ig.

Current, LNC and Zen 5 have similar 1T perf.
In 2026 with Zen 6, Lets say NVL ST is only 10% better than ARL, and Zen 6 is 30% better than Zen 5, through some combination of IPC and Fmax improvements. Would be a very large 20% gap.
In 2027 lets say Griffin Cove is still only another 10% improvement over Cougar? Panther? whatever NVL's P-core is. They are now ~10% behind AMD.
In 2028 Zen 7 and hopefully unified core would be out. ~10% is the gap that Intel will be facing, spit balling a pretty bad case for Intel.

I mean you could still talk to him on reddit lol, he is active there...

Certainly, yes Zen5 is more complete in terms of architecture than Lion Cove.
but In terms of performance, LNC and Zen5 are evenly matched
Also, personally, I think the challenge is that the interconnect technology is immature rather than the physical FOVEROS technology.
Rather, it seems that FOVEROS has a high degree of perfection.

 

[DavidC1]

The perf improvement was supposedly 40%, the IPC was supposedly double.

Which is not that impressive for a huge core with revolutionary ideas in 2028.

The biggest contention of the P-cores isn't even area (though that is bad), it's the equally bad power consumption.
Area is arguably the least important part of the PPA consideration, and Apple's very large cores should be a real life example that if a core is large, much better perf and power could make it viable.

They go together, because it means more transistors. And Apple cores are smaller too, while being faster and lower power.

With IPC that high and clocks looking to be that low, the power efficiency of this core likely would have blown anything else away. I imagine in server it would esentially be running at Vmin at extremely high perf/watt.
Further iterations of RYC were supposedly going to improve perf/mm2, but even the rumor iteration sounds like it would be viable enough...

I'm guessing it was less engineering decisions that caused RYC to be canned, but financial and political ones.

Or... it was a disappointment.

Surprising then Jim Keller joined the board of that company, despite also being the CEO of another risc-v company that also is aimed to produce high performance risc-v cores.

Given his history with Intel, I would imagine he had to seriously believe in the viability of the core and the people behind it in order to do this.

It also assumes he is infallible.

Also, they were talking about how Skymont was targetted by Keller to go head to head against Zen 5. And the "12-wide" core he was said to be working on is likely Arctic Wolf.

 

[Io Magnesso]

Worth noting that TSMC didn't have to pay $28B. Anyone who wanted to reserve volume had to pay up front. A lot of that $28B came from Apple, etc. Cashflow solves a lot of funding problems. Apple typically runs upward of $40B in prepayments across their supply chain which buys a lot of manufacturing capacity. Intel would operate the same way, but with the challenge that whoever is making that investment has to have faith that Intel will be able to deliver. That's a big part of the current problem - customers are going to want a discount because Intel is unproven as a foundry (and is known for having a haughty attitude toward customers), and Intel can't really afford a discount. Federal programs can only carry you so far.

No, Apple didn't pay for the factory.
Naturally, TSMC paid all the costs of the factory construction. That's a matter of course
Certainly, if you say that the money that Apple paid to TSMC is being used to build the factory, you can see it.
You're trying to tie it to Apple right away...

 

[Io Magnesso]

Which is not that impressive for a huge core with revolutionary ideas in 2028.

They go together, because it means more transistors. And Apple cores are smaller too, while being faster and lower power.

Or... it was a disappointment.

It also assumes he is infallible.

Also, they were talking about how Skymont was targetted by Keller to go head to head against Zen 5. And the "12-wide" core he was said to be working on is likely Arctic Wolf.

It's true that even if Jim Keller isn't directly involved in the development of the architecture.

It cannot be denied that Jim Keller may be indirectly involved in building the architecture by advising the e-core team.

 

[johnsonwax]

No, Apple didn't pay for the factory.
Certainly, if you say that the money that Apple paid to TSMC is being used to build the factory, you can see it.
You're trying to tie it to Apple right away...

I didn't say Apple paid for the whole factory. But ok, where do prepayment funds go then? What does TSMC use that money for that they get before production starts?

Have you tracked any of Apples prepayment agreements in the past? I have. Several of them.

 

[Io Magnesso]

The perf improvement was supposedly 40%, the IPC was supposedly double.
The biggest contention of the P-cores isn't even area (though that is bad), it's the equally bad power consumption.
Area is arguably the least important part of the PPA consideration, and Apple's very large cores should be a real life example that if a core is large, much better perf and power could make it viable.
With IPC that high and clocks looking to be that low, the power efficiency of this core likely would have blown anything else away. I imagine in server it would esentially be running at Vmin at extremely high perf/watt.
Further iterations of RYC were supposedly going to improve perf/mm2, but even the rumor iteration sounds like it would be viable enough...

I'm guessing it was less engineering decisions that caused RYC to be canned, but financial and political ones.

Yes, I was referring to PTL's die area of all the tiles.
Actually, looking back at that document leak, PTL's active tile area is only ~220mm2.

Surprising then Jim Keller joined the board of that company, despite also being the CEO of another risc-v company that also is aimed to produce high performance risc-v cores.
Given his history with Intel, I would imagine he had to seriously believe in the viability of the core and the people behind it in order to do this.

Idk how much of ARL's problems coming from the packaging being suboptimal, vs the fabric itself just being very bad. We might see in NVL ig.

Current, LNC and Zen 5 have similar 1T perf.
In 2026 with Zen 6, Lets say NVL ST is only 10% better than ARL, and Zen 6 is 30% better than Zen 5, through some combination of IPC and Fmax improvements. Would be a very large 20% gap.
In 2027 lets say Griffin Cove is still only another 10% improvement over Cougar? Panther? whatever NVL's P-core is. They are now ~10% behind AMD.
In 2028 Zen 7 and hopefully unified core would be out. ~10% is the gap that Intel will be facing, spit balling a pretty bad case for Intel.

I mean you could still talk to him on reddit lol, he is active there...

Exist50 Is that person?
Are you the one who always said that ARC was abolished?

 

[Io Magnesso]

I didn't say Apple paid for the whole factory. But ok, where do prepayment funds go then? What does TSMC use that money for that they get before production starts?

Have you tracked any of Apples prepayment agreements in the past? I have. Several of them.

Some? , Is it just about "some"?
Is that all?
It's enough, I'm tired
Why so much...? Do you want to push Apple to the front? It's not just Apple, customers
Well, I haven't heard that the cost of building a TSMC factory comes from a customer's advance payment… Where is the evidence?