Intel's Nehalem IMC...

[EdzAviator]

We all knew why AMD have very little L2 Cache compare to current Intel cpu....

It's because AMD said that with their IMC, there is really no need for as much as larger cache as current Intel's C2D & C2Q..

But Intel's Nehalem still have a large cache even if they have an IMC....

Will it mean that Intel will extend the lead much more with the IMC and large cache working together..???

Or there is no performance differences if for example a Nehalem quad w/ 8MB Cache and a Nehalem quad w/ 4MB Cache...???

How will AMD counter the large cache of Intel, while current Phenom's Cache is just 512 L2 per core and unified 2MB L3...???

 

[Borealis7]

Originally posted by: EdzAviator

We all knew why AMD have very little L2 Cache compare to current Intel cpu....

It's because AMD said that with their IMC, there is really no need for as much as larger cache as current Intel's C2D & C2Q..

And look where it got them...

But all jokes aside, we cant know. We can only speculate, but based on past experience we have a baseline to evaluate Intel CPUs. for instance, the E6x20 series had larger cache than the regular E6x00 series and about 5% better performance.

so if we see somehting new from AMD (lol?) before Nehalem we could try and guess how will it do against it.

 

[soccerballtux]

I imagine their prefetch/branch prediction code is so good we're not going to see a huge jump in performance from the integrated controller. If we were going to see one, then going from 2->4MB would probably have a made a difference. Also if there were going to be a big performance jump, I think they would stop talking about Nehalim now and wouldn't bring anything new out until AMD got back on their feet (actually I wish they would do this so that AMD would have more time to catch up again and not get too much into debt.)

 

[BitByBit]

AMD will go down the same 'large cache + IMC' route as Intel with the introduction of Montreal, which will, if rumour is to be believed, have 1MB L2 per core and 6MB L3 per die. An IMC does not, per the misconception, eliminate the benefit of larger cache. An IMC reduces the impact of memory access, but memory access is still undesirable from a performance perspective.

Any performance increases from Nehalem on the desktop will have less to do with its IMC and more to do with core enhancements. The server platform will be an entirely different story however.

 

[nonameo]

The biggest benefit for intel is in ditching the FSB for multi-processor systems.

 

[Nemesis 1]

I would like very much to see A link from intel that states this. Nehalem will have L3 shared cache. As I understand it the desktop will have L1 semi shared cache and L2 Completely shared L2 cache. So a link from Intel talking about L# shared cache please.

All I have read is multilevel shared cache. L1& L2

 

[Nemesis 1]

Originally posted by: BitByBit
AMD will go down the same 'large cache + IMC' route as Intel with the introduction of Montreal, which will, if rumour is to be believed, have 1MB L2 per core and 6MB L3 per die. An IMC does not, per the misconception, eliminate the benefit of larger cache. An IMC reduces the impact of memory access, but memory access is still undesirable from a performance perspective.

Any performance increases from Nehalem on the desktop will have less to do with its IMC and more to do with core enhancements. The server platform will be an entirely different story however.

Well since intel is coming out with 3 differant sockets for Nehalem . One without IMC we will get to test your theory.

 

[taltamir]

AMD just couldnt afford to put extra cache on because they are alwys behind in their manufacturing process... so they use the IMC that reduces the benfit of cache a bit, but it does not eliminate it, the benefit still exists.

 

[Nemesis 1]

If one looks at the slides for Nehalem the transitor count shows completely that NO transitors are being used for Nehalem L3 cache . Penryn has more transitors than nehalem the reson for fewer transitors on Nehalem is the smaller L2 cache size. So its plain as dirt that Intel has not accounted for L3 transitor count on an l3 cache. So there for the multi level caches are L1 and L2. Unless you can show me a transitor bidget for L# cache on nehalem core.

 

[Nemesis 1]

Originally posted by: soccerballtux
I imagine their prefetch/branch prediction code is so good we're not going to see a huge jump in performance from the integrated controller. If we were going to see one, then going from 2->4MB would probably have a made a difference. Also if there were going to be a big performance jump, I think they would stop talking about Nehalim now and wouldn't bring anything new out until AMD got back on their feet (actually I wish they would do this so that AMD would have more time to catch up again and not get too much into debt.)

Why would Intel slow down tick tock to wait on AMD? Intel is in the chip business to make money. The sooner they transition to 32nm from 45nm . More profits for Intel . Shrinking the process isn't about beating AMD to 32nm . Its about Productivity. Intel cann't simply step on the breaks .
TO gett from 45nm to 32nm . will go penryn / nehalem 45-32nm . / Geshner 32-22nm.

Intel is locked into this cadence. TO get to 32nm. Comes Nehalem @ 45. To get to 22nm Intel gesher @ 32nm.

Intel surely isn't going to stop moores law for AMD.

 

[Phynaz]

Originally posted by: Nemesis 1
If one looks at the slides for Nehalem the transitor count shows completely that NO transitors are being used for Nehalem L3 cache . Penryn has more transitors than nehalem the reson for fewer transitors on Nehalem is the smaller L2 cache size. So its plain as dirt that Intel has not accounted for L3 transitor count on an l3 cache. So there for the multi level caches are L1 and L2. Unless you can show me a transitor bidget for L# cache on nehalem core.

You're assuming that Nehalem is Penryn + IMC.

 

[Nemesis 1]

No . Nehalem will have a max of 8mb L2 Cache . Penryn has 12mb L2 cache. Yet Nehalem Has Only a little less total transitors per 4core. So You consider the transitor count of the 4mb cache advantage Penryn has . It pretty clear Intel added alot of logic transitors. + IMC transitor count+ Quick Path . SO its plane NO L3 ON the Desktop.

INTEL has clearly said that Nehalem will have multi level shared cache on the Desktop. And will also have L3 cache. 24mb. On the high end server . IF you look at Nehalems roadmap . It only shows Topend server with L3 cache. ALL OTHER L1 L2

 

[SexyK]

Where did anyone say Nehalem was going to have an L3 cache?

 

[Phynaz]

Originally posted by: Nemesis 1
No . Nehalem will have a max of 8mb L2 Cache . Penryn has 12mb L2 cache. Yet Nehalem Has Only a little less total transitors per 4core. So You consider the transitor count of the 4mb cache advantage Penryn has . It pretty clear Intel added alot of logic transitors. + IMC transitor count+ Quick Path . SO its plane NO L3 ON the Desktop.

INTEL has clearly said that Nehalem will have multi level shared cache on the Desktop. And will also have L3 cache. 24mb. On the high end server . IF you look at Nehalems roadmap . It only shows Topend server with L3 cache. ALL OTHER L1 L2

You're still trying to determine the feature set of Nehalem by couning Penryn's transistors.

Can you see where that is not logical?

 

[myocardia]

Originally posted by: SexyK
Where did anyone say Nehalem was going to have an L3 cache?

Right here was the first time it was mentioned:

Originally posted by: Nemesis 1
I would like very much to see A link from intel that states this. Nehalem will have L3 shared cache. As I understand it the desktop will have L1 semi shared cache and L2 Completely shared L2 cache. So a link from Intel talking about L# shared cache please.

 

[Nemesis 1]

. I may be mistaken it could be XS or .But I am sure that people here were discussing Intels L3Cache here in other threads. I am fairly certain that intels L1 cache will be semi shared and L2 will be completely shared.

Has their ever been a Cpu with shared L1 cache?

 

[Borealis7]

Originally posted by: Nemesis 1
. I may be mistaken it could be XS or << .But I am sure that people here were discussing Intels L3Cache here in other threads. I am fairly certain that intels L1 cache will be semi shared and L2 will be completely shared.

Has their ever been a Cpu with shared L1 cache?

Riiiii-ght. sure! we believe ya! yeah we can hear the voices too! pfftt....i've just heard the voices like a minute ago...

(*picks up phone...dials 9-1-1 slowly...*)

 

[VirtualLarry]

I don't see how L1 cache could be shared effectively, without making performance tank. I don't see how it would be large enough for there to be a benefit to sharing it either. And L3 cache for Nehalem? That's news to me.