Chip Architect
More at site.Three clues for Yamhill seem to provide substantial prove.
The industry has speculated a year now on the existence of 64 bit extensions to the x86 ISA in Intel's future 90 nm processor codenamed Prescott. We could show in our March 6 article that Prescott contains two instead of one 32 bit integer execution cores. The question arises for the purpose of such a second core? In fact there are many different possibilities: Use it to run a separate trace to improve hyper threading. Use it to check the results of the first core (IBM has a processor that does just this). And of course, Yamhill is just one of them. searching for clues we started looking at the highest resolution die-plot of the Pentium 4 we could find and try if we could make some sense of all these little artificial colored rectangles and lines. (The photo shows 5 micrometer details) We made progress, studied code optimization manuals for clues, Went through all the presentations, then looked at Pentium 4 related patents from known P4 architects, made more progress, gained confidence and started to write an article about the Integer execution core with the die photo as the visual base. This long article will be published in the near future. For now we have stumbled on a number of clues that seem to provide substantial prove for the existence of Yamhill. If (or when) it will be enabled is a different question. They might even call it the Pentium 6.... (Tejas = 7, Nehalem = 8 )
( Edit, March 29,2003: The rumors are that it will be enabled in Potomac.
The MP version for systems with more than 2 processors in late 2004 )
And then now the clues, They are handled in more in detail later in the article.
Clue 1: The second Integer Unit has no AGU's (Fast double clocked Address Generator Units)
This unit provides the address bits 32 and higher. We will show that there is no need to provide these bits very fast
in the NetBurst Architecture with its replay capabilities. nor do we need all bit 32 through 63 A virtual address size of 40 or 48 bits would be sufficient for the time being. (It's 48 bits in the first implementation of the Hammer family)
Clue 2: The second Integer Unit register file has a smaller size, 1.30 x 0.64 mm versus 1.30 x 0.71 mm
The (renamed) register file of the Pentium 4 has 128 entries for 32 bit data plus 6 bit status flags. We could show that Prescott has two 256 entry register files. The width of both are the same meaning that they have the same number of entries. The height of the second one is less however indicating that there are less data bits. We presume that it has all its 32 data bits but that the 6 status flags are lacking. A 64 bit processor needs only one set of status flags per 64 bit word. This clue also implies that the second core can not be used to run an independent 32 bit thread.
Clue 3: The data caches have been shifted in order to balance critical path in 64 bit processing
The first core has to provide the address bits for the data caches of both cores. Most critical in Northwood are bits 6..11 that select one of 32 cache lines in a 2k page and bits 12..16 that are used to predict which of the 4 ways contains the cache line (4 x 2kByte = 8 kByte cache size). These paths should be as short as possible. Going from one core to another introduces a long path for a critical signal. However, it turns out that the path to both caches are equal in length. The managed this by shifting both caches upwards. (see second image below)
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