They could clock Gen 12 LP higher on 10SF (seen on DG1) but they would lose efficiency which is very important for an ULV Soc. Also they wouldn't gain a lot of performance because it's bandwidth starved, on ADL-P DDR5 this should change. DG1 has latency penalties over the iGPU version, LPDDR4x isn't fast enough to compensate for this. And yes the posted lineup doesn't make sense. In the driver leak back in 2019 only three options were listed: 128/256/512.