Intel to debut next generation chip design at IDC !!!

[Dothan]

HERE is the link !!!

might we see Conroe with HT support ?

these are exciting times in cpu industry !!! intel already has scored with new 65nm yonah parts yielding higher than expected and stomping all over Turion !!! can't wait to see these at retail !!!

now we have a lot of conroe rumor and speculative things but my bet is we see HT/SSE2/SSE3 and starting frequencies over 2GHz !!!

 

[Viditor]

LOLOLOLOLOLOL!!!

1. How can you have high yields before you go into production?
2. Yonah isn't out, so the only way it "stomps all over Turion" is through your imagination (which appears to be fixed on only one thing...)
3. The P-M architecture has a real problem with H-T...
4. There is still no demonstrated way to get 64bit on the PM architecture
5. Starting frequencies had BETTER be over 2.0 Ghz in order to even compete with the Sempron...

 

[Capt Caveman]

How about a link to your new rig? And benchmarks? Loser. Troll.

 

[BitByBit]

Even if this is Conroe they're debuting in two weeks, AMD has little to worry about, as it isn't expected to be released for atleast another year.
Conroe will very likely far exceed the K8 in average IPC performance if it is, according to rumour, a wide-issue design, while being as efficient as the current Pentium M.
Being a 'wider' design will mean that it will be well-suited to SMT; the reason Banias/Dothan aren't suitable is because they are both narrow designs, and achieve average IPC very close to their maximum already.
A four-issue x86 architecture will actually need SMT to keep those execution units busy, as extracting that much ILP from single threads would prove to be difficult.

When Conroe is finally released however, it will be facing high-clocked K8s. If Intel can scale up Conroe's clock speeds sufficiently quickly, then AMD may be prompted to released K10 early. We can only speculate on the K10's architecture, given AMD's traditional secrecy, but I'd be willing to bet AMD have a few surprises in store.

 

[Keysplayr]

Originally posted by: Viditor
LOLOLOLOLOLOL!!!

1. How can you have high yields before you go into production? True.

2. Yonah isn't out, so the only way it "stomps all over Turion" is through your imagination (which appears to be fixed on only one thing...)Yonah does not have to stomp all over the Turion because the Dothan does that already.

3. The P-M architecture has a real problem with H-T... Maybe that's because the P-M does not have HT maybe? :roll:

4. There is still no demonstrated way to get 64bit on the PM architecture Your acting like it can't be done. Wassup with that?

5. Starting frequencies had BETTER be over 2.0 Ghz in order to even compete with the Sempron...

Sempron?!? LOL!!! You mean FX57!!.

Seriously though, after seeing your "LAPTOP" thread, I can't take you literally as you tend to stretch things a bit.

 

[Pabster]

Another thread meant to incite a riot.

And Vidi, since when was Pentium-M (or Yonah, or Conroe) competing with a SEMPRON?

 

[Viditor]

Originally posted by: keysplayr2003

Originally posted by: Viditor
LOLOLOLOLOLOL!!!

1. How can you have high yields before you go into production? True.

2. Yonah isn't out, so the only way it "stomps all over Turion" is through your imagination (which appears to be fixed on only one thing...)Yonah does not have to stomp all over the Turion because the Dothan does that already.

3. The P-M architecture has a real problem with H-T... Maybe that's because the P-M does not have HT maybe? :roll:

4. There is still no demonstrated way to get 64bit on the PM architecture Your acting like it can't be done. Wassup with that?

5. Starting frequencies had BETTER be over 2.0 Ghz in order to even compete with the Sempron...

Sempron?!? LOL!!! You mean FX57!!.

Seriously though, after seeing your "LAPTOP" thread, I can't take you literally as you tend to stretch things a bit.

Geez keys...can't you take a joke? (laptop thread)
I meant the Semprons that will be released when Conroe is, mate...or do you think AMD is gonna stay with these speeds for the next 1.5 years?

 

[Viditor]

Originally posted by: Pabster
Another thread meant to incite a riot.

And Vidi, since when was Pentium-M (or Yonah, or Conroe) competing with a SEMPRON?

Ummm...they do make Sempron notebooks...

 

[Viditor]

Originally posted by: BitByBit
Even if this is Conroe they're debuting in two weeks, AMD has little to worry about, as it isn't expected to be released for atleast another year.
Conroe will very likely far exceed the K8 in average IPC performance if it is, according to rumour, a wide-issue design, while being as efficient as the current Pentium M.
Being a 'wider' design will mean that it will be well-suited to SMT; the reason Banias/Dothan aren't suitable is because they are both narrow designs, and achieve average IPC very close to their maximum already.
A four-issue x86 architecture will actually need SMT to keep those execution units busy, as extracting that much ILP from single threads would prove to be difficult.

When Conroe is finally released however, it will be facing high-clocked K8s. If Intel can scale up Conroe's clock speeds sufficiently quickly, then AMD may be prompted to released K10 early. We can only speculate on the K10's architecture, given AMD's traditional secrecy, but I'd be willing to bet AMD have a few surprises in store.

Nice post 3B...one other thing to consider is that the FSB on the Conroe and even the follow-on Cloverton (quad-core) will be a max of 1066. That's gonna be one heck of a bottleneck!

 

[BitByBit]

Intel will probably compensate with larger caches for the time being, reducing the need for a faster FSB. However, AMD has shown the way with their memory interface, and it is time for Intel to ditch the old external arrangement, which is what may happen when they introduce their CSI design, whenever it is they intend to.
But yes, quad-core CPUs will be very bandwidth-starved using an external FSB, and quad cores with 2-4MB L2 caches will create huge dies and prove costly, 65nm or not.
AMD will be able to get away with smaller caches, thanks to their superior memory interface, giving them an edge in costs.

 

[Viditor]

Originally posted by: BitByBit
Intel will probably compensate with larger caches for the time being, reducing the need for a faster FSB. However, AMD has shown the way with their memory interface, and it is time for Intel to ditch the old external arrangement, which is what may happen when they introduce their CSI design, whenever it is they intend to.

I believe they have pushed CSI to the end of 2007. The word is that they reassigned CSI resources for Conroe, Merom, and especially Paxville, so they could get them out on/ahead of schedule. Intel is losing an awful lot of marketshare to Opteron right now...
You may be right on the increased cache, but that won't help when 4 cores need to access memory. It's not just the cache coherency...

Besides, adding cache is an expensive fix!

 

[miketheidiot]

Originally posted by: BitByBit
Even if this is Conroe they're debuting in two weeks, AMD has little to worry about, as it isn't expected to be released for atleast another year.
Conroe will very likely far exceed the K8 in average IPC performance if it is, according to rumour, a wide-issue design, while being as efficient as the current Pentium M.
Being a 'wider' design will mean that it will be well-suited to SMT; the reason Banias/Dothan aren't suitable is because they are both narrow designs, and achieve average IPC very close to their maximum already.
A four-issue x86 architecture will actually need SMT to keep those execution units busy, as extracting that much ILP from single threads would prove to be difficult.

When Conroe is finally released however, it will be facing high-clocked K8s. If Intel can scale up Conroe's clock speeds sufficiently quickly, then AMD may be prompted to released K10 early. We can only speculate on the K10's architecture, given AMD's traditional secrecy, but I'd be willing to bet AMD have a few surprises in store.

i thought p-m was a 3 issue, like k7/k8/etc

 

[BitByBit]

The P6's decoders can issue just over two instructions per clock on average to its two ALUs or single FPU.
I'm not sure about MMX/SSE, but it's the number of integer/floating-point units that matter. They determine the maximum IPC the core can achieve when executing most code, while the processor's efficiency determines how often they're kept busy.

 

[Keysplayr]

Originally posted by: Viditor

Originally posted by: keysplayr2003

Originally posted by: Viditor
LOLOLOLOLOLOL!!!

1. How can you have high yields before you go into production? True.

2. Yonah isn't out, so the only way it "stomps all over Turion" is through your imagination (which appears to be fixed on only one thing...)Yonah does not have to stomp all over the Turion because the Dothan does that already.

3. The P-M architecture has a real problem with H-T... Maybe that's because the P-M does not have HT maybe? :roll:

4. There is still no demonstrated way to get 64bit on the PM architecture Your acting like it can't be done. Wassup with that?

5. Starting frequencies had BETTER be over 2.0 Ghz in order to even compete with the Sempron...

Sempron?!? LOL!!! You mean FX57!!.

Seriously though, after seeing your "LAPTOP" thread, I can't take you literally as you tend to stretch things a bit.

Geez keys...can't you take a joke? (laptop thread)
I meant the Semprons that will be released when Conroe is, mate...or do you think AMD is gonna stay with these speeds for the next 1.5 years?

LOL brudda, of course. I didn't mean anything by it, just trying to continue it. Cheers mate!

 

[DarkKnight69]

Dothan will beat almost EVERY processor single threaded (ie Gaming) clock for clock. Yonah will be a nice processor even if it does not have HT (Dual core annyways).

If you are saying that it will suck cuz it is intel, you are wrng, go look at benchies of single thread Dothan performance and you will see.

 

[Pabster]

Originally posted by: Viditor

Originally posted by: Pabster
Another thread meant to incite a riot.

And Vidi, since when was Pentium-M (or Yonah, or Conroe) competing with a SEMPRON?

Ummm...they do make Sempron notebooks...

Of course they do. At very low price points. It is a VALUE chip...

My point is that AMD won't be comparing a Sempron laptop to a Conroe-based one. 😀
(unless you'd like to compare a current Sempron laptop to a Dothan-based one 😛)

 

[bjc112]

My point is that AMD won't be comparing a Sempron laptop to a Conroe-based one.

Agreed.