Intel Tells 7700k Owners to Stop Overclocking to Avoid High Temps

[moonbogg]

That toothpaste is crap. I won't buy coffee lake for sure if it has that junk TIM under the hood.

 

[crashtech]

That toothpaste is crap. I won't buy coffee lake for sure if it has that junk TIM under the hood.

Yeah, well, that's what it's going to have...

 

[TheELF]

soldered CPU seems to be working fine on AMD's FX line space heaters, no pun intended.

Those are allowed what, 65-70°C before they completely shut down?
So less heat less problems?
What no igpu to add to the heat/space problem?
Oh,they also have like twice the area?

 

[IEC]

Unless you are using LN2, the use of solder should not be an issue. It does preclude safe/reliable delidding, but in normal and even overclocked operation users will not have the rapid and extreme temperature swings necessary to create voids in the solder material.

 

[Agent-47]

Those are allowed what, 65-70°C before they completely shut down?
So less heat less problems?
What no igpu to add to the heat/space problem?
Oh,they also have like twice the area?

and your point is? micro cracks will occur due to stress caused by rapid spike/fluctuations temps. the magnitude of the spike and the freq are the main concerns and not the maximum attainable temp, there are solder pads that work just fine at 200C. true, the lower limit will mean lower magnitude of the spike, but i am yet to see any CPU jump from 30 C to 70C in less than one-second. so it means nothing.

last i checked, AMD also has CPU+iGPU configs. which ironically uses solder pads. having said that a iGPU free CPU on its own can draw more power than CPU+iGPU. unless after all these years you want to say FX line runs cooler than intel. is that what you mean?

what does die area have to do with anything, unless you want to say the rise time of the spike are long enough for the heat to be spread out throughout the entire CPU, which is not the case, as you will see that cpu core temps can vary based on CPU usage even after prolonged single threaded load

EDIT: https://www.youtube.com/watch?v=Hf8V_UulpBk
look at that guy poking at the silicon with a razor. silicon being a hard substance is not damaged from this, and yet it will break up due to a microcrack?

 

[TheELF]

and your point is? micro cracks will occur due to stress caused by rapid spike/fluctuations temps. the magnitude of the spike and the freq are the main concerns and not the maximum attainable temp, there are solder pads that work just fine at 200C. true, the lower limit will mean lower magnitude of the spike, but i am yet to see any CPU jump from 30 C to 70C in less than one-second. so it means nothing.

Look at previous page convienently posted by tamz_msc jumps from below 30 to above 70...

last i checked, AMD also has CPU+iGPU configs. which ironically uses solder pads. having said that a iGPU free CPU on its own can draw more power than CPU+iGPU.

Do I seriously have to search for a die size pic of APU now?
246 on line with sandy the last die that had solder for intel according to previous posts.

unless after all these years you want to say FX line runs cooler than intel. is that what you mean?

You are forced to cool them harder,which makes the cooler blow more heat into your room,yes.

what does die area have to do with anything, unless you want to say the rise time of the spike are long enough for the heat to be spread out throughout the entire CPU, which is not the case, as you will see that cpu core temps can vary based on CPU usage even after prolonged single threaded load

Read the link I posted, the TIM forms cracks not the silicon,exactly because most of the time only some areas of the chip get hot at any o time the TIM at that spot gets hotter then the rest of the TIM repeat for hundreds of cycles and the TIM weakens at those spots with cracks being the result.

Void and micro crack occurrence is mainly affected by the solder area – thus the DIE size. Small DIE size (below 130 mm²) e. g. Skylake will facilitate the void occurence significantly. However, CPUs with a medium to large DIE size (above 270 mm²) e. g. Haswell-E show no significant increase of micro cracking during thermal cycling (Figure 12).

 

[tamz_msc]

What's interesting is that in the official specifications, Intel lists the Tcase when it comes to the 3770K, 4770K, 4790K and 6700K. It's only in the case of the 7700K that Tjunction is specified instead of Tcase.

 

[LTC8K6]

What's interesting is that in the official specifications, Intel lists the Tcase when it comes to the 3770K, 4770K, 4790K and 6700K. It's only in the case of the 7700K that Tjunction is specified instead of Tcase.

I can see from XTU that my 4790K throttles right at 99-100C core temp on the nose. 🙂

 

[Agent-47]

1. Look at previous page convienently posted by tamz_msc jumps from below 30 to above 70...

2. Do I seriously have to search for a die size pic of APU now?
246 on line with sandy the last die that had solder for intel according to previous posts.

3. You are forced to cool them harder,which makes the cooler blow more heat into your room,yes.

4. Read the link I posted, the TIM forms cracks not the silicon,exactly because most of the time only some areas of the chip get hot at any o time the TIM at that spot gets hotter then the rest of the TIM repeat for hundreds of cycles and the TIM weakens at those spots with cracks being the result.

1. so? its showing the 7700 which has problems.
2. Yes, you the one arguing wihout any proof or real life demonstration what so ever
3. So?
4. So? read the link yourself please: "thermal cycle is performed by going from -55 °C to 125 °C while each temperature is hold [held] for 15 minutes" very realistic. don't quote academic studies, find me a "small" CPU that failed. Let me sort you out a little: AMD Athlon 64 is 103.1 mm² and a Max temp of 78 C. so now you know what CPU you have to find that developed a crack!

 

[TheELF]

4. So? read the link yourself please: "thermal cycle is performed by going from -55 °C to 125 °C while each temperature is hold [held] for 15 minutes" very realistic. don't quote academic studies, find me a "small" CPU that failed. Let me sort you out a little: AMD Athlon 64 is 103.1 mm² and a Max temp of 78 C. so now you know what CPU you have to find that developed a crack!

Yes the test scenario for failure prediction is unrealistic that's how every stress test for any material or product is being done.
If a company would make a small chip with solder and even one of them would show signs of something like this then the mass law suits would still quote these academic studies,real life chances of this happening don't matter, companies cover their asses.

 

[IEC]

That guy poking the chip is der8auer. He killed 2 of 3 chips when he tried the initial delid with Ryzen. His follow-up video examining the effects showed a 1°C drop in maximum temperature using liquid metal direct die cooling versus AMD's soldered IHS, indicating AMD did a very good job with the solder and that delid is completely unnecessary (and ill advised) for Ryzen:
https://youtu.be/wz_-Q5QzRqg?t=433

Proper solder application is great for CPU cooling. It would be nice if Coffee Lake has a better TIM solution than the 7700K. Which wouldn't seem that hard to do, because the 7700K's TIM solution is apparently the worst of all the Intel chips thus far per Silicon Lottery's delid improvement numbers. And we know solder is possible for Coffee Lake given that Ryzen is using solder at its small die size. At the very least they could use a thinner application of TIM if they aren't going to solder.

 

[tamz_msc]

I don't buy the argument that there are issues if you try to use solder instead of thermal paste for smaller dies. Here is my testing done on an ancient Core 2 Duo E6300 on a stock heatsink that hasn't been replaced in 10 years, in 35+ degree Celsius ambient temperatures. For anyone wondering, the E6300 is only 143mm^2 'small'. OCCT doesn't keep the load at 100% for some reason, but it doesn't throttle. TjMax is 85 degrees.

I don't think that the spikes on the 7700K can be explained by Speed Shift or Turbo, doesn't OCCT make the CPU run at it's maximum frequency during the test?

 

[LTC8K6]

KL may simply have a better sensor that is more accurate and responds quicker.

 

[tamz_msc]

KL may simply have a better sensor that is more accurate and responds quicker.

Over a long time scale if there were short duration spikes they might not be pick up by the OCCT graph. This isn't the case however.

 

[jpiniero]

You'd think people would know by now that AVX2 causes Core to become a space heater, esp at 4+ Ghz.

 

[tamz_msc]

You'd think people would know by now that AVX2 causes Core to become a space heater, esp at 4+ Ghz.

People are reporting these spikes with CPU:OCCT. Does it use AVX2? I'm pretty sure if they used LINPACK which does support AVX2 their CPUs would shut down in minutes.

 

[scannall]

I wonder if there is a problem with specific batches. Reports seem all over the place.

 

[Agent-47]

You'd think people would know by now that AVX2 causes Core to become a space heater, esp at 4+ Ghz.

Intel CPUs down clock themselves when it is running AVX codes irrespective of temps. So the effect should be not be anything that is different from normal usage.
http://www.anandtech.com/show/10158/the-intel-xeon-e5-v4-review/3

one AVX instruction on one core forced all cores on the same socket to slow down their clockspeed by around 2 to 4 speed bins (-200,-400 MHz) for at least 1 ms,

 

[jpiniero]

Intel CPUs down clock themselves when it is running AVX codes irrespective of temps. So the effect should be not be anything that is different from normal usage.

I'd have to think that doesn't apply when OCing unless you use the AVX offset.

 

[Agent-47]

That guy poking the chip is der8auer. He killed 2 of 3 chips when he tried the initial delid with Ryzen.

while he did not specify how he killed his other 2 chips, i believe he specifically mentioned about registers and caps on the edge of the pcb, which i believe he nicked accidentally as he did not know they were there.

silicon crystalline, which is used to make the wafers have a hardness of 6.5MPa. or an absolute hardness of 974 kg/mm2. compared to diamond, which is 10 MPa, it is certainly not as hard and is possible to break it if you are wielding a hammer. However I doubt very much it is possible to even scratch it with a razor unless he was really having a go at it with all his might. 🙂

I'd have to think that doesn't apply when OCing unless you use the AVX offset.

Cannot find the link now, but it becomes unstable at high clocks which is why you have an AVX offset which downclocks the chip even when you OC. if you read the quote it says "slow down their clockspeed by around 2 to 4 speed bins"

 

[tamz_msc]

I'd have to think that doesn't apply when OCing unless you use the AVX offset.

Separate multipliers for AVX workloads were introduced in the E5 2600v3. AVX offset is a feature in the BIOS introduced with Z270. http://www.intel.com/content/dam/ww...on-e5-v3-advanced-vector-extensions-paper.pdf

 

[w3rd]

What design/node will be going into Intel's new HEDT chips..?

 

[LTC8K6]

People are reporting these spikes with CPU:OCCT. Does it use AVX2? I'm pretty sure if they used LINPACK which does support AVX2 their CPUs would shut down in minutes.

I would think a LINPACK shutdown problem for KL would have been big news long ago...as would a loss of throttle ability...